PIC16LF1526-I/MR Microchip Technology, PIC16LF1526-I/MR Datasheet - Page 98

• Manufacturer Part Number: PIC16LF1526-I/MR
• Description: MCU PIC 14KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1526-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C
• Maximum Clock Frequency: 20 MHz
• Number Of Timers: ÿ6 x 8-bit, 3 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16(L)F1526/27
10.1
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 25.0 “Electrical Specifications”
LFINTOSC tolerances.
10.2
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See
10.2.1
When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.
WDT protection is active during Sleep.
10.2.2
When the WDTE bits of Configuration Word 1 are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
10.2.3
When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See
Table 10-1
TABLE 10-1:
TABLE 10-2:
DS41458A-page 98
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Change INTOSC divider (IRCF bits)
WDTE<1:0>
Independent Clock Source
WDT Operating Modes
11
10
01
00
for more details.
WDT IS ALWAYS ON
WDT IS OFF IN SLEEP
WDT CONTROLLED BY SOFTWARE
Table
WDT OPERATING MODES
WDT CLEARING CONDITIONS
10-1.
SWDTEN
X
X
1
0
X
Conditions
Device
Awake
Mode
Sleep
X
X
X
Disabled
Disabled
Disabled
Active
Active
Active
Mode
for the
WDT
Preliminary
10.3
The WDTPS bits of the WDTCON register set the
time-out period from 1ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
10.4
The WDT is cleared when any of the following condi-
tions occur:
• Any Reset
• CLRWDT instruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail event
• WDT is disabled
• OST is running
See
10.5
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See
Module (With Fail-Safe Clock Monitor)”
information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See
The
information.
Table 10-2
STATUS
Time-Out Period
Clearing the WDT
Operation During Sleep
Section 3.0 “Memory Organization”
for more information.
register
Cleared until the end of OST
 2011 Microchip Technology Inc.
(Register
Section 5.0 “Oscillator
Unaffected
Cleared
WDT
3-1)
for
for more
more
and