SI3050-E-FT Silicon Laboratories Inc, SI3050-E-FT Datasheet - Page 42
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SI3050-E-FT
Manufacturer Part Number
SI3050-E-FT
Description
IC VOICE DAA GCI/PCM/SPI 20TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-KT.pdf
(112 pages)
Specifications of SI3050-E-FT
Package / Case
20-TSSOP (0.173", 4.40mm Width)
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Function
Data Access Arrangement (DAA)
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Product
RF / Wireless
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current
8.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3050-E-FT
Manufacturer:
Silicon Labs
Quantity:
1 794
Part Number:
SI3050-E-FTR
Manufacturer:
SILICONI/矽睿科技
Quantity:
20 000
Si3050 + Si3018/19
5.33. Companding in PCM Mode
The
companding formats in addition to 16-bit linear data.
The 8-bit companding schemes follow a segmented
curve formatted as a sign bit, three chord bits, and four
step bits. µ-Law is commonly used in North America
and Japan, while A-Law is primarily used in Europe.
Data format is selected via the PCMF bits (Register 33).
Table 21 on page 43 and Table 22 on page 44 define
the µ-Law and A-Law encoding formats. If linear mode
is used the resulting 16-bit data is transmitted in two
consecutive 8-bit PCM highway timeslots as shown in
Figure 32.
42
PCLK_CNT
FSYNC
PCLK
DRX
Si3050
DTX
Figure 32. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
Figure 33. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
PCLK_CNT
HI-Z
0
FSYNC
supports
PCLK
MSB
MSB
DRX
1
DTX
2
3
HI-Z
(TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11, HSSM = 1)
4
5
both
0
(TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11)
6
Sample 1
MSB
MSB
7
1
µ-Law
8
2
9
10
3
11
and
12
4
13
5
14
A-Law
15
6
Rev. 1.31
16
17
7
5.34. 16 kHz Sampling Operation in PCM
The Si3050 can be configured to support a 16 kHz
sampling rate and transmit the data on an 8 kHz PCM or
GCI
(Register 7, bit 3) to 1, the DAA changes its sampling
rate, Fs, to 16 kHz if it was originally configured for an
8 kHz sampling rate. If µ-law or A-law companding is
used, the resulting 8-bit samples are transmitted in two
consecutive 8-bit PCM highway timeslots. If linear mode
is used, the resulting 16-bit samples are transmitted in
four consecutive 8-bit PCM highway timeslots as shown
in Figure 33.
18
8
19 20
Mode
9
highway
21
10
22
Sample 2
23
11
24
12
bus.
25
HI-Z
26
13
27
By
28
14
29
15
setting
30
LSB
LSB
31
16
LSB
LSB
32
33
17
the
34
HI-Z
18
35
HSSM
36 37
bit