SI3050-E-FT Silicon Laboratories Inc, SI3050-E-FT Datasheet - Page 62
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SI3050-E-FT
Manufacturer Part Number
SI3050-E-FT
Description
IC VOICE DAA GCI/PCM/SPI 20TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-KT.pdf
(112 pages)
Specifications of SI3050-E-FT
Package / Case
20-TSSOP (0.173", 4.40mm Width)
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Function
Data Access Arrangement (DAA)
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Product
RF / Wireless
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current
8.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3050-E-FT
Manufacturer:
Silicon Labs
Quantity:
1 794
Part Number:
SI3050-E-FTR
Manufacturer:
SILICONI/矽睿科技
Quantity:
20 000
Si3050 + Si3018/19
Register 3. Interrupt Mask
Reset settings = 0000_0000
62
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
LCSOM
DODM
RDTM
ROVM
TGDM
FDTM
BTDM
POLM
Name
RDTM
R/W
D7
Ring Detect Mask.
0 = A ring signal does not cause an interrupt on the AOUT/INT pin.
1 = A ring signal causes an interrupt on the AOUT/INT pin.
Receive Overload Mask.
0 = A receive overload does not cause an interrupt on the AOUT/INT pin.
1 = A receive overload causes an interrupt on the AOUT/INT pin.
Frame Detect Mask.
0 = The ISOcap losing frame lock does not cause an interrupt on the AOUT/INT pin.
1 = The ISOcap losing frame lock causes an interrupt on the AOUT/INT pin.
Billing Tone Detect Mask.
0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.
1 = A detected billing tone causes an interrupt on the AOUT/INT pin.
Drop Out Detect Mask.
0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.
1 = A line supply dropout causes an interrupt on the AOUT/INT pin.
Loop Current Sense Overload Mask.
0 = An interrupt does not occur when the LCS bits are all 1s.
1 = An interrupt occurs when the LCS bits are all 1s.
TIP Ground Detect Mask.
0 = The TGD bit going active does not cause an interrupt on the AOUT/INT pin.
1 = The TGD bit going active causes an interrupt on the AOUT/INT pin.
Polarity Reversal Detect Mask (Si3019 line-side only).
This interrupt is generated from bit 7 of the LVS register. When this bit transitions, it indicates
that the polarity of TIP and RING is switched.
0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.
1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.
ROVM
R/W
D6
FDTM
R/W
D5
Rev. 1.31
BTDM
R/W
D4
Function
DODM
R/W
D3
LCSOM
R/W
D2
TGDM
R/W
D1
POLM
R/W
D0