TWR-ADCDAC-LTC Freescale Semiconductor, TWR-ADCDAC-LTC Datasheet - Page 44

• Manufacturer Part Number: TWR-ADCDAC-LTC
• Description: MOD ADC DAC TOWER LINEAR TECH
• Manufacturer: Freescale Semiconductor
• Type: A/Dr

Specifications of TWR-ADCDAC-LTC

• Main Purpose: Data Conversion, ADC, DAC
• Embedded: No
• Utilized Ic / Part: LTC1859, LTC2498, LTC2600, LTC2704, LTC3471
• Primary Attributes: 2 Analog to Digital Converters, 2 Digital to Analog Converters
• Secondary Attributes: For use with Freescale Tower System
• Maximum Clock Frequency: 50 MHz
• Interface Type: Touch Sense, ULPI, UART, IrDA, I2S,
• Product: Data Conversion Development Tools
• Silicon Manufacturer: Freescale
• Silicon Core Number: LTC2704, LTC2600, LTC1859, LTC2498, LTC3471 & LTC6655-5
• Kit Application Type: Data Converter
• Application Sub Type: ADC, DAC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Kinetis MCU
• Lead Free Status / Rohs Status: Compliant

16 or 32 channel implementation that performs complex data transfers with minimal CPU intervention
Programmable source and destination addresses and transfer size
Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
Channel activation via one of three methods:
Fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
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Number of channels depends on the specific Kinetis device
Connections to the crossbar switch for bus mastering the data movement
All data movement via dual-address transfers: read from source, write to destination
Internal data buffer used a temporary storage to support 16-byte burst transfers
Support for enhanced addressing modes
Supports 8-bit, 16-bit, 32-bit, and 16-byte transfer sizes
32-byte TCD stored in local memory for each channel
An inner data transfer loop defined by a minor byte transfer count
An outer data transfer loop defined by a major iteration count
Explicit software initiation
Initiation via a channel-to-channel linking mechanism for continuous transfers
Peripheral-paced hardware requests (one per channel)
Support for cancelling transfers via hardware or software
One interrupt per channel, optionally asserted at completion of major iteration count
Optional error terminations per channel and logically summed together to form
One error interrupt to the interrupt controller
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Support for scatter/gather DMA processing
Support for complex data structures
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DMA Features
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