TWR-ADCDAC-LTC Freescale Semiconductor, TWR-ADCDAC-LTC Datasheet - Page 45
TWR-ADCDAC-LTC
Manufacturer Part Number
TWR-ADCDAC-LTC
Description
MOD ADC DAC TOWER LINEAR TECH
Manufacturer
Freescale Semiconductor
Type
A/Dr
Specifications of TWR-ADCDAC-LTC
Main Purpose
Data Conversion, ADC, DAC
Embedded
No
Utilized Ic / Part
LTC1859, LTC2498, LTC2600, LTC2704, LTC3471
Primary Attributes
2 Analog to Digital Converters, 2 Digital to Analog Converters
Secondary Attributes
For use with Freescale Tower System
Maximum Clock Frequency
50 MHz
Interface Type
Touch Sense, ULPI, UART, IrDA, I2S,
Product
Data Conversion Development Tools
Silicon Manufacturer
Freescale
Silicon Core Number
LTC2704, LTC2600, LTC1859, LTC2498, LTC3471 & LTC6655-5
Kit Application Type
Data Converter
Application Sub Type
ADC, DAC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Kinetis MCU
Lead Free Status / Rohs Status
Compliant
Region Descriptors
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Error Reporting
Access Control
Region Sizes
Mechanism
Feature
Resources
Protected
Rights
•
port) capture the last faulting address,
Core Masters: read, write, and execute
Multiple error registers (one per slave
•
Up to 8 AHB Master Connections:
32 byte to 4 GB; allows overlapping
•
•
IPS is protected by AIPS Controller
attributes for supervisor and user
Generates access protection error
Non-core Masters: read and write
master number, attributes, etc.
•
•
SRAM via crossbar switch
DRAM Controller (3 ports)
•
•
FSL MPU
TCMU SRAM
TCML SRAM
protection
accesses
•
attributes
Up to 16
FlexBus
•
Flash
FSL MPU vs. ARM MPU
•
Up to 8; each with 8 equal sub-regions
•
Read, write, and execute attributes for
Single error registers capture the last
32 byte to 4 GB; allows overlapping
•
Generates access protection error
46
46
faulting address, attributes, etc.
supervisor and user accesses
(MemManage Fault Handler)
•
•
SRAM via crossbar switch
DRAM Controller (3 ports)
ARM MPU
•
TCMU SRAM
Core Only:
protection
•
FlexBus
•
IPS
TM