LMK04000BEVAL/NOPB National Semiconductor, LMK04000BEVAL/NOPB Datasheet - Page 3

• Manufacturer Part Number: LMK04000BEVAL/NOPB
• Description: BOARD EVAL PRECISION CLOCK PLL
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMK04000BEVAL/NOPB

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK04000
• Primary Attributes: 122.88 MHz VCXO
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK04000BEVAL; LMK04000BEVAL

The LMK040xx Evaluation Board simplifies evaluation of the LMK040xx Precision Clock Conditioner with Dual
PLLs and Integrated VCO.
Semiconductor’s CodeLoader software, which can be downloaded from the following URL:
http://www.national.com/analog/timing/codeloader
The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader software is used
to program the internal registers of the LMK040xx device through a MICROWIRE
The following block diagram illustrates the functional architecture of the LMK040xx clock conditioner. It features
a cascaded, dual PLL arrangement, available internal loop filter components for PLL2, internal VCO with PLL2
for frequency synthesis, and clock distribution section with individual channel dividers and delay adjustment
blocks. The dual reference clock input to PLL1 provides fail-safe redundancy for phase locked loop operation.
The cascaded PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that
contains excessive phase noise. This requires the user to select an external oscillator (VCXO or crystal) that
provides the desired phase noise performance at the output of the clock channels. This external oscillator
becomes the reference clock for PLL2 and along with the phase noise characteristics of PLL2 and the internal
VCO, determines the final phase noise performance at F
PLL1 has been designed to work with either an off-the-shelf VCXO package or with a user-designed discrete
implementation that employs a crystal resonator and associated tuning components. The following block
diagram shows an example of a discretely implemented VCXO using a crystal resonator.
Figure 1. Functional Block Diagram of the LMK040xx Dual PLL Precision Clock Conditioner with External
CLKin0
CLKin1
DATA
CLK
LE
Interface
uWire
R
1
L M K 0 4 0 X X
PLL1
vcxo
N
1
Configuring and controlling the board is accomplished using National
E V A L U A T I O N
General Description
R
2
PLL2
VCXO module.
B O A R D
N
3
2
OUT
CHAN
CHAN
DIV
DIV
and the output of the clock distribution section.
VCO
DIV
O P E R A T I N G
LVPECL, LVDS,
5 Output Clock
VCO
Channels
LVCMOS
I N S T R U C T I O N S
TM
interface.
CLKout_0
CLKout_4
F
OUT