ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 20

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Configurability and Communication
I2E can respond to status queries, be turned on and
turned off, and generally configured via SPI
programmable registers. Configuring of I2E is generally
unnecessary unless the application cannot meet the
requirements of Track Mode on or after power up.
Parameters that can be adjusted and read back include
FS/4 filter threshold and status, Power Meter threshold
and status, and initial values for the offset, gain, and
sample time values to use when I2E starts.
1
2
3
CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP
Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization
CLKDIVRSTP
Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay t
Sample Clock
Analog Input
ADC1 CLKOUTP
ADC2 CLKOUTP
ADC2 CLKOUTP
20
Input
(phase 2)
(phase 1)
ADC1 Output Data
ADC2 Output Data
2
FIGURE 37. SYNCHRONOUS RESET OPERATION
3
3
s1
s2
ISLA112P50
L+t
t
RSTH
s0
Clock Divider Synchronous
Reset
An output clock (CLKOUTP, CLKOUTN) is provided to
facilitate latching of the sampled data. This clock is at
half the frequency of the sample clock, and the absolute
phase of the output clocks for multiple A/Ds is
indeterminate. This feature allows the phase of multiple
A/Ds to be synchronized (refer to Figure 37), which
greatly simplifies data capture in systems employing
multiple A/Ds.
The reset signal must be well-timed with respect to the
sample clock (See “Switching Specifications” on page 9).
s0
d
1
t
RSTS
s1
s1
s2
s2
s3
s3
d
t
RSTRT
June 17, 2010
FN7604.1