ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 27

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of setting these options is different from the other
registers.
The procedure for setting output_mode_B is shown in
Figure 45. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The ISLA112P50 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing.
A static word can be placed on the output bus, or two
different words can alternate. In the alternate mode, the
values defined as Word 1 and Word 2 (as shown in
Table 14) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to “SPI Memory Map” on
page 28.
OUTPUT_MODE_B
CONFIG_STATUS
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
FIGURE 45. SETTING OUTPUT_MODE_B REGISTER
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
READ
READ
0x74
0x75
TABLE 14. OUTPUT TEST MODES
Negative Full-Scale
Positive Full-Scale
OUTPUT TEST
Checkerboard
User Pattern
DESIRED
0xC0[3:0]
VALUE
One/Zero
Reserved
Reserved
Midscale
MODE
Off
27
user_patt1 user_patt2
WORD 1
0xAAAA
0x8000
0x0000
0xFFFF
0xFFFF
N/A
N/A
WRITE TO
WORD 2
0x74
0x5555
0x0000
ISLA112P50
N/A
N/A
N/A
N/A
N/A
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Digital Temperature Sensor
This set of registers provides digital access to an
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die. This information is
of particular interest for applications that do not keep I2E
in Active Run state when in normal use, allowing easy
access to information that can be used to decide when to
recalibrate the A/D as needed. This set of registers is not
included in the SPI memory map table.
The most accurate usage of this information requires
knowledge of the temperature at which the digital value
is first read (time = 0, T(0) = degrees C at time = 0, and
register_value(0) = the digital value of the temperature
registers at time = 0). Any future reading of the registers
indicates temperature change according to Equation 4:
ΔT
A less accurate method for evaluating the temperature
change does not require knowledge of the temperature
at time = 0, and is given by Equation 5:
ΔT
The digital temperature sensor is a weak function of the
AVDD supply voltage, so to achieve best accuracy the
AVDD supply voltage should be held fairly constant
across the operarating temperature range.
The algorithm to access this set of registers is as follows:
1. Write the value 0x80 to the Index Register (SPI
2. Write the value 0x88 to SPI address 0x120 to turn
3. Read the register_value LSBs at SPI register 0x11E
4. Read the register_value MSBs at SPI register 0x11F
5. Write the value 0x60 to SPI address 0x120 to turn
=
=
address 0x10)
the temperature sensor on.
the temperature sensor off.
T 1 ( ) T 0 ( )
T 1 ( ) T 0 ( )
–
–
=
=
[
---------------------------------------------------------------------------------------------------------------- -
[
---------------------------------------------------------------------------------------------------------------- -
register_value(1)
register_value(1)
[
(
T 0 ( ) 216
(
–
-0.72
]
]
–
–
[
[
register_value(0)
register_value(0)
)
) 256
⁄
]
June 17, 2010
FN7604.1
(EQ. 4)
(EQ. 5)
]
]