LAN9218-MT SMSC, LAN9218-MT Datasheet - Page 119

• Manufacturer Part Number: LAN9218-MT
• Description: CONTROLLER, ENET, 10/100, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9218-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
6.2
SYMBOL
t
t
cycle
t
t
t
t
t
csdv
t
t
LAN9218
asu
don
doff
doh
csh
nCS, nRD
csl
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.1 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
DATASHEET
119
MIN
45
32
13
0
0
0
0
TYP
Revision 1.93 (11-27-07)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns