PCA9555PW NXP Semiconductors, PCA9555PW Datasheet - Page 7
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PCA9555PW
Manufacturer Part Number
PCA9555PW
Description
IC, I2C-BUS AND SMBUS I/O PORT, TSSOP24
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9555BS118.pdf
(34 pages)
Specifications of PCA9555PW
Chip Configuration
16 Bit
Bus Frequency
400kHz
Ic Interface Type
I2C
No. Of I/o's
16
Supply Voltage Range
2.3V To 5.5V
Digital Ic Case Style
TSSOP
No. Of Pins
24
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PCA9555PW
Manufacturer:
NXP
Quantity:
3 125
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Part Number:
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Manufacturer:
NXP Semiconductors
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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Company:
Part Number:
PCA9555PW/G
Manufacturer:
MPS
Quantity:
23 062
Part Number:
PCA9555PW/G118
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
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Manufacturer:
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Quantity:
20 000
Part Number:
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Manufacturer:
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Quantity:
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NXP Semiconductors
PCA9555_8
Product data sheet
6.2.2 Registers 0 and 1: Input port registers
6.2.3 Registers 2 and 3: Output port registers
6.2.4 Registers 4 and 5: Polarity Inversion registers
This register is an input-only port. It reflects the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 5.
Table 6.
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined
as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
Table 7.
Table 8.
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 9.
Table 10.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Input port 0 Register
Input port 1 register
Output port 0 register
Output port 1 register
Polarity Inversion port 0 register
Polarity Inversion port 1 register
O0.7
O1.7
N0.7
N1.7
I0.7
I1.7
X
X
7
7
7
1
7
1
7
0
7
0
Rev. 08 — 22 October 2009
O0.6
O1.6
N0.6
N1.6
I0.6
I1.6
X
X
6
6
6
1
6
1
6
0
6
0
O0.5
O1.5
N0.5
N1.5
I0.5
I1.5
X
X
5
5
5
1
5
1
5
0
5
0
16-bit I
O0.4
O1.4
N0.4
N1.4
I0.4
I1.4
X
X
4
4
4
1
4
1
4
0
4
0
2
C-bus and SMBus I/O port with interrupt
O0.3
O1.3
N0.3
N1.3
I0.3
I1.3
X
X
3
3
3
1
3
1
3
0
3
0
O0.2
O1.2
N0.2
N1.2
I0.2
I1.2
2
X
2
X
2
2
2
2
1
1
0
0
PCA9555
© NXP B.V. 2009. All rights reserved.
O0.1
O1.1
N0.1
N1.1
I0.1
I1.1
X
X
1
1
1
1
1
1
1
0
1
0
O0.0
O1.0
N0.0
N1.0
I0.0
I1.0
X
X
0
0
0
1
0
1
0
0
0
0
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