OX16C950-TQBG OXFORD SEMICONDUCTOR, OX16C950-TQBG Datasheet - Page 31
![IC, UART, 1CH, SMD, TQFP48, 950](/photos/19/3/190350/42334692_sml.jpg)
OX16C950-TQBG
Manufacturer Part Number
OX16C950-TQBG
Description
IC, UART, 1CH, SMD, TQFP48, 950
Manufacturer
OXFORD SEMICONDUCTOR
Datasheet
1.OX16C950-TQBG.pdf
(50 pages)
Specifications of OX16C950-TQBG
No. Of Channels
1
Data Rate
15Mbps
Uart Features
Tx/Rx FIFO INT TRIG
Supply Voltage Range
3V To 5.25V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
No. Of Pins
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
OX16C950-TQBG
Manufacturer:
SAMSUNG
Quantity:
450
14
14.1
The UART contains a programmable baud rate generator
that is capable of taking any clock input from DC to 60MHz
(at 5V) and dividing it by any 16-bit divisor number from 1
to 65535 written into the DLM (MSB) and DLL (LSB)
registers. In addition to this, a clock prescaler register is
provided which can further divide the clock by values in the
range 1.0 to 31.875 in steps of 0.125. Also, a further
feature is the Times Clock Register ‘TCR’ which allows the
sampling clock to be set to any value between 4 and 16.
These clock options allow for highly flexible baud rate
generation capabilities from almost any input clock
frequency (up to 60MHz). The actual transmitter and
receiver baud rate is calculated as follows:
Where:
SC
Divisor
Prescaler = 1 when MCR[7] = ‘0’ else:
M
N
See next section for a discussion of the clock prescaler and
times clock register.
After a hardware reset, the prescaler is bypassed (set to 1)
and TCR is set to 0x00 (i.e. SC = 16). Assuming this
default configuration, the following table gives the divisors
required to be programmed into the DLL and DLM registers
in order to obtain various standard baud rates:
DS-0031 Sep 05
BaudRate
OXFORD SEMICONDUCTOR LTD.
B
AUD
General Operation
= Sample clock values defined in TCR[3:0]
= DLL + ( 256 x DLM )
= M + ( N / 8 ) where:
= CPR[7:3] (Integer part – 1 to 31)
= CPR[2:0] (Fractional part – 0.000 to 0.875 )
R
=
ATE
SC
*
G
Divisor
ENERATION
InputClock
*
prescaler
External—Free Release
Table 15: Standard PC COM Port Baud Rate Divisors
DLM:DLL
Divisor Word
(assuming a 1.8432MHz crystal)
0x00C0
0x000C
0x0900
0x0300
0x0180
0x0060
0x0030
0x0018
0x0006
0x0004
0x0003
0x0002
0x0001
Baud Rate
(bits per second)
OX16C950 rev B
115,200
19,200
28,800
38,400
57,600
1,200
2,400
4,800
9,600
110
300
600
50
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