OX16C950 OXFORD [Oxford Semiconductor], OX16C950 Datasheet
OX16C950
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OX16C950 Summary of contents
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... Transmitter and receiver can be disabled NHANCEMENTS The OX16C950B is an enhanced, fully backward-compatible revision of the OX16C950 rev A. The chief enhancements are as follows – • All known errata fixed • Enhanced features first offered in OX16PCI954 added – these include controls for sleep-mode sensitivity, ability to read FCR and Good Data Status • ...
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... ISDN terminal adapters also suitable for any equipment requiring high speed RS232/RS422/RS485 interfaces. Fabricated in 0.6µm process, OX16C950 also has a low operating current and sleep mode for battery powered applications. Oxford Semiconductor 2001 OX16C950 rev B Datasheet R1.2 – May 2001 ...
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... BAND LOW 14 BAUD RATE GENERATION.................................................................................................................................................... 30 14 .......................................................................................................................................................... 30 ENERAL PERATION 14 ‘CPR’.................................................................................................................................... 31 LOCK RESCALER EGISTER 14 ‘TCR’............................................................................................................................................. 31 IMES LOCK EGISTER 14 ........................................................................................................................................................ 33 NPUT LOCK PTIONS 14.5 TTL C M ........................................................................................................................................................... 33 LOCK ODULE Data Sheet Revision 1.2 ‘EFR’................................................................................................................................ 28 ......................................................................................................................................... 29 ................................................................................................................................... 29 C ........................................................................................................................... 29 ONTROL OX16C950 rev B Page 3 ...
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... PERATION 18 AC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 42 18 .................................................................................................................................................................... 42 PERATION 18 .................................................................................................................................................................... 43 PERATION 19 TIMING WAVEFORMS............................................................................................................................................................. 44 20 PACKAGE INFORMATION...................................................................................................................................................... 46 21 ORDERING INFORMATION .................................................................................................................................................... 47 NOTES............................................................................................................................................................................................ 48 CONTACT DETAILS ...................................................................................................................................................................... 49 Data Sheet Revision 1.2 ............................................................................................................................................ 33 ‘ASR’................................................................................................................................... 34 ‘ACR’................................................................................................................................ 34 ‘TTL’..................................................................................................................................... 36 L ‘RTL’ ....................................................................................................................... 36 EVEL ...................................................................................................................................... 36 ‘GDS’ .............................................................................................................................. 39 ‘CKA’............................................................................................................................... 39 OX16C950 rev B Page 4 ...
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... Software reset Device ID 9-bit data frames RS485 buffer enable Infra-red (IrDA) Table 1 OX16C950 performance compared with 16C450, 16C550, 16C650 and 16C750 devices Improvements of the OX16C950 over previous generations of PC UART: Deeper FIFOs: OX16C950 offers 128-byte deep FIFOs for the transmitter and receiver. ...
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... OX16C950 device to software drivers. Infra-red ‘IrDA’ interface: The UART contains an IrDA compliant modulator and demodulator. 9-bit data framing: The OX16C950 may be configured to use in 9-bit character framing for multi-drop protocols where a tag ID (9 differentiates address and data characters. Control and Status ...
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... Pin Thin Quad Flat Pack OX16C950-TQC60 OX16C950 rev RESET 39 OUT1# 38 DTR# 37 RTS OUT2# 34 INTSEL# 33 INT 32 RXRDY INTSEL# 36 RESET ...
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... GND. Eight-bit 3-state data bus. Drive Disable. This pin goes active (high) when CPU is not reading from OX16C950. This signal can be used to disable an external transceiver. Active-low write strobe. When IOW# is used to write the chip, IOW should be tied low (inactive). ...
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... BDOUT# to the RCLK pin or setting CKS[1:0] to ’10’ where BDOUT# will be connected to RCLK internally. In this case setting CKS[2] to ‘1’ will disable the BDOUT# pin to conserve power. Receiver clock. RCLK is the Nx (usually 16x, see TCR) baud rate clock for the receiver. OX16C950 rev B Page 9 ...
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... When low (or unconnected), 5V biased TTL thresholds are used. When high, 3V biased TTL thresholds are used. Generally should be tied high when the OX16C950 is being powered off 3 Volts, and low (or unconnected) when powered off 5 Volts. If tied high under 5V operation, CMOS compatible input thresholds are obtained. ...
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... Connect to a suitable line driver Connect to a suitable line receiver Connect to a suitable line driver Connect to a suitable line receiver OX16C950 rev B Action when not used Tie high – All chip selects must be active in order to access the device Tie high – All chip selects must be active in order to access the device Tie low – ...
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... Interrupt Output Data Sheet Revision 1.2 Action when used Connect to a suitable line receiver Connect to a suitable line receiver Connect to an available processor interrupt line OX16C950 rev B Action when not used Tie high Tie high Leave unconnected (Interrupts can not be used) Page 12 ...
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... The OX16C950 device is a single channel device software compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the OX16C950 depends on a number of mode settings. These modes are referred to throughout this data sheet. The FIFO depth and compatibility modes are tabulated below: ...
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... It is also possible to define the over-sampling rate used by the transmitter and receiver clocks. The 16C450/16C550 and compatible devices employ 16 times over-sampling, i.e. There are 16 clock cycles per bit. However, OX16C950 can employ any over-sampling rate from programming the TCR register. This allows the data rates to be increased to 460 ...
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... DSR CTS Temporary data storage register and Indexed control register offset value bits Unused Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte) Table 4: Standard 550 Compatible Registers OX16C950 rev B Bit 3 Bit 2 Bit 1 Data received Modem Rx Stat THRE ...
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... Char Detect Number of characters in the receiver FIFO Number of characters in the transmitter FIFO Data read/written depends on the value written to the SPR prior to the access of this register (see Table 6: 950 Specific Registers OX16C950 rev B Bit 3 Bit 2 Bit 1 Bit 0 In-band flow control mode Bit 3 ...
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... Unused Force Force TxRdy RxRdy inactive inactive Hardwired Port Index ( 0x00 ) Unused Output sys-clk on txrdy Table 7: Indexed Control Register Set ). 2 OX16C950 rev B Bit 3 Bit 2 Bit 1 Auto Tx control DSR Disable Flow Control Enable 3 Bit “fractional” part of clock prescaler 4 Bit N-times clock ...
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... Read the desired value from ICR (address 101 Write 0x00 offset to SPR to select ACR. Clear bit 6 of ACR bye writing x0xxxxxx Data Sheet Revision 1 address 101 . Ensure that other bits in ACR are not changed ICR, thus enabling access to standard registers again. 2 OX16C950 rev B Page 18 ...
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... Data Sheet Revision 1.2 OX16C950 rev B Software Reset 7.2 An additional feature available in the OX16C950 device is software resetting of the serial channel. The software reset is available using the CSR register. Software reset has the same effect as a hardware reset except it does not reset the clock source selections (i.e. CKS register and CKA register). To reset the UART write 0x00 to the Channel Software Reset register ‘ ...
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... FCR[5] increases the FIFO size. 450, 550 and extended 550 modes: The transmitter interrupt trigger levels are set to 1 and FCR[5:4] are ignored. OX16C950 rev B manner as FCR[1] does for the RHR. Page 20 ...
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... Writing the value 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. 550 FIFO Size n/a 1 n/a 4 n/a 8 n/a 14 OX16C950 rev B C & S ONTROL TATUS Page 21 ...
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... LSR. LSR[5]: THR empty logic 0 ⇒ Transmitter FIFO (THR) is not empty. logic 1 ⇒ Transmitter FIFO (THR) is empty. OX16C950 rev B overrun error has occurred. The error is flagged when the data would normally have been transferred to the RHR. received data is ‘0’ in 9-bit mode. ...
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... Enable alternate sleep mode whereby the In 16C750 compatible mode (i.e. non-Enhanced mode), this bit is used an alternate sleep mode and has the same effect as IER[4]. (See section 10.4) OX16C950 rev B bit) set can generate the channel is switched off. internal clock of the channel is switched off. ...
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... FIFO and transmitter shift register are empty and the SOUT line has returned to idle marking state. OX16C950 rev B Interrupt Description data bit) interrupt by th data bit). ...
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... OUT2#) are set in-active (high), and the receiver inputs SIN, CTS#, DSR#, DCD#, and RI# are all disabled. Internally the transmitter output is connected to the receiver input and DTR#, RTS#, OUT1# and OUT2# are connected to modem status inputs DSR#, CTS#, RI# and DCD# respectively. the OX16C950 rev B Page 25 ...
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... MCR[7] is loaded with the complement of the CLKSEL pin. User writes to this flag will only take effect in enhanced mode. See section 13.1. Data Sheet Revision 1.2 OX16C950 rev B Modem Status Register ‘MSR’ 11.2 MSR[0]: Delta CTS# Indicates that the CTS# input has changed since the last time the MSR was read ...
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... Where divisor is given by DLL + ( 256 x DLM ). More flexible baud rate generation options are also available. See section 14 for full details. Data Sheet Revision 1.2 OX16C950 rev B Scratch Pad Register ‘SPR’ 12.2 The scratch pad register does not affect operation of the rest of the UART in any way and can be used for temporary data storage ...
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... XOFF2 as valid XOFF characters when EFR[3:2] = “01” or “10”. EFR[1:0] should not be set to “11” when EFR[3:2] is either “00”. Data Sheet Revision 1.2 OX16C950 rev B EFR[3:2]: In-band transmit flow control mode When in-band transmit flow control is enabled, an XON/XOFF character is inserted into the data stream whenever the RFL passes the upper trigger level and falls below the lower trigger level respectively ...
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... Data Sheet Revision 1.2 OX16C950 rev B When the 'XON Any' flag (MCR[5]) is set, any received character is accepted as a valid XON condition and the transmitter will be re-enabled. The received data will be transferred to the RHR ...
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... TCR is set to 0x00 (i. 16). Assuming this default configuration, the following table gives the divisors required to be programmed into the DLL and DLM registers in order to obtain various standard baud rates: Data Sheet Revision 1.2 OX16C950 rev B DLM:DLL Baud Rate Divisor Word (bits per second) ...
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... Table 18 on the following page. These are the values in bits-per-second (bps) that are obtained if the divisor latch = 0x01 and the Prescaler is set to 1. The OX16C950 has the facility to operate at baud-rates Mbps at 5V. The table below indicates how the value in the register corresponds to the number of clock cycles per bit ...
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... OX16C950 rev B Max. Baud rate Max. Baud rate with CPR = 1, with CPR = 1, TCR = 16 ...
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... The industry standard system clock for PC COM ports is 1.8432 MHz, limiting the maximum baud rate to 115.2 Kbps. The OX16C95x UARTs support system clocks up to 50MHz (60MHz for the OX16C950 at 5V) and its flexible baud rate generation hardware means that almost any frequency can be optionally scaled down for compatibility with standard devices ...
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... This can be used to determine whether a level 5 interrupt was caused by receiving a special character rather than an XOFF. The flag is cleared following the read of the ASR. Data Sheet Revision 1.2 OX16C950 rev B ASR[5]: FIFOSEL This bit reflects the unlatched state of the FIFOSEL pin. ASR[6]: FIFO size logic 0 ⇒ ...
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... When the transmitter is empty the DTR# would go inactive once the SOUT line returns to it’s idle marking state. Data Sheet Revision 1.2 OX16C950 rev B ACR[5]: 950 mode trigger levels enable logic 0 ⇒ Interrupts and flow control trigger levels are as described in FCR register and are compatible with 16C650/16C750 modes. logic 1 ⇒ ...
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... The device ID registers may be read using offset values 0x08 to 0x0B of the Indexed Control Register. Registers ID1, ID2 and ID3 identify the device as an OX16C950 and return 0x16, 0xC9 and 0x50 respectively. The REV register resides at offset 0x0B of ICR and identifies the revision of 950 core ...
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... Interrupts in 9-Bit Mode: While IER[2] is set, upon receiving a character with status error, a level 1 interrupt is asserted when the character and the associated status are transferred to the FIFO. The OX16C950 can assert an optional interrupt if a received character has its 9 bit set. As multi-drop systems th ...
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... The above facility produces an interrupt for recognizing any ‘address’ characters. Alternatively, the user can configure OX16C950 to match the receiver data stream with up to four programmable 9-bit characters and assert a level 5 interrupt after detecting a match. The interrupt occurs when the character is transferred to the FIFO (See below) ...
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... Port Index Register ‘PIX’ 15.14 The PIX register is located at offset 0x12 of the ICR. This read-only register gives the UART index. For a single channel device such as the OX16C950 this reads ‘0’. Clock Alteration Register ‘CKA’ 15.15 The CKA register is located at offset 0x13 of the ICR. This register adds additional clock control mainly for isochronous and embedded applications ...
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... current 1.8432 MHz 7.372 MHz 60.00 MHz 1.8432 MHz 7.372 MHz 60.00 MHz CK Table 22: DC Electrical Characteristics OX16C950 rev B Min. Max. Units -0.3 7 +/- 10 mA -40 125 °C Min Max Units 3 5. °C Min. ...
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... current 1.8432 MHz 7.372 MHz 60.00 MHz 1.8432 MHz 7.372 MHz 60.00 MHz CK Table 23: DC Electrical Characteristics OX16C950 rev B Min. Max. Units 3.0 3. TBD TBD -0.5 0 TBD TBD 5 µA ...
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... In this case the mark-to-space ratio is 50/50 for the purpose of set-up and hold calculations. Data Sheet Revision 1.2 Note1 Note1 Note1 Note1 Note2 Note3 Table 24: AC Electrical Characteristics OX16C950 rev B Min Max Units ...
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... In this case the mark-to-space ratio is 50/50 for the purpose of set-up and hold calculations. Data Sheet Revision 1.2 Note1 Note1 Note1 Note1 Note2 Note3 Table 25: AC Electrical Characteristics OX16C950 rev B Min Max Units ...
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... Address Valid De-asserted Asserted t acc Data Valid Figure 4: Read Cycle Timing sac Address Valid De-asserted Asserted Data Valid Figure 5: Write Cycle Timing OX16C950 rev B t had t hac De-asserted had t hac t ha ...
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... OXFORD SEMICONDUCTOR LTD. SIN Rx_Clk_In (DSR#) SOUT Tx_Clk_Out (DTR#) Data Sheet Revision 1.2 t irs t its Figure 6: Isochronous Mode Timing OX16C950 rev B t irh Page 45 ...
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... OXFORD SEMICONDUCTOR LTD ACKAGE NFORMATION OX16C950-PCC60-B Data Sheet Revision 1.2 Figure 7: 44 Pin Plastic Leaded Chip Carrier OX16C950 rev B Page 46 ...
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... OXFORD SEMICONDUCTOR LTD. OX16C950-TQC60 RDERING NFORMATION OX16C950-PCC60-B Revision Operating Conditions -Commercial Package Type - OX16C950-TQC60-B Revision Package Material - P lastic Package Type - Data Sheet Revision 1.2 Figure 8: 48 Pin Thin Quad Flat Pack (48 TQFP) OX16C950 rev B Page 47 ...
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... OXFORD SEMICONDUCTOR LTD. N OTES Data Sheet Revision 1.2 This page has intentionally been left blank. OX16C950 rev B Page 48 ...
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C D ONTACT ETAILS Oxford Semiconductor Ltd. 25 Milton Park Abingdon Oxfordshire OX14 4SH United Kingdom Telephone: +44 (0)1235 824900 Fax: +44 (0)1235 821141 Sales e-mail: sales@oxsemi.com Web site: http://www.oxsemi.com ©Copyright Oxford Semiconductor Ltd 1998-2001 Oxford Semiconductor Ltd believes the ...