OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet
OX16PCI954-TQC60-A
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OX16PCI954-TQC60-A Summary of contents
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... The OX16PCI954 also provides an IEEE1284 EPP parallel port which fully supports the existing Centronics interface. The parallel port can be enabled in place of the Local Bus. Oxford Semiconductor 1999 OX16PCI954 Data Sheet Revision 1.3 – Feb. 1999 Part No. OX16PCI954-TQC60-A serial EEPROM. ...
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... MODE ............................................................................................................................................................ 29 7.1.3 EXTENDED 550 MODE......................................................................................................................................... 29 7.1.4 750 MODE ............................................................................................................................................................ 29 7.1.5 650 MODE ............................................................................................................................................................ 29 7.1.6 950 MODE ............................................................................................................................................................ 30 7.2 REGISTER DESCRIPTION TABLES ......................................................................................................................... 31 7.3 RESET CONFIGURATION ........................................................................................................................................ 34 7.3.1 HARDWARE RESET ............................................................................................................................................. 34 7.3.2 SOFTWARE RESET.............................................................................................................................................. 34 7.4 TRANSMITTER AND RECEIVER FIFOS ................................................................................................................... 35 7.4.1 FIFO CONTROL REGISTER ‘FCR’ ........................................................................................................................ 35 7.5 LINE CONTROL & STATUS...................................................................................................................................... 36 7.5.1 FALSE START BIT DETECTION ........................................................................................................................... 36 Data Sheet Revision 1.3 OX16PCI954 Page 2 ...
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... PARALLEL PORT INTERRUPT ................................................................................................................................ 53 9.3 REGISTER DESCRIPTION........................................................................................................................................ 54 9.3.1 PARALLEL PORT DATA REGISTER ‘PDR’ ........................................................................................................... 54 9.3.2 DEVICE STATUS REGISTER ‘DSR’ ...................................................................................................................... 54 9.3.3 DEVICE CONTROL REGISTER ‘DCR’................................................................................................................... 55 9.3.4 EPP ADDRESS REGISTER ‘EPPA’ ....................................................................................................................... 55 9.3.5 EPP DATA REGISTERS ‘EPPD1-4’ ....................................................................................................................... 55 9.3.6 EXTENDED CONTROL REGISTER ‘ECR’ ............................................................................................................. 55 Data Sheet Revision 1.3 OX16PCI954 Page 3 ...
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... ZONE3: PCI CONFIGURATION REGISTERS ........................................................................................................ 58 11 OPERATING CONDITIONS .................................................................................................................. ELECTRICAL CHARACTERISTICS ..............................................................................................59 12.1 NON-PCI I/O BUFFERS............................................................................................................................................. 59 12.2 PCI I/O BUFFERS ..................................................................................................................................................... ELECTRICAL CHARACTERISTICS ..............................................................................................61 13.1 PCI BUS.................................................................................................................................................................... 61 13.2 LOCAL BUS.............................................................................................................................................................. 61 13.3 SERIAL PORTS ........................................................................................................................................................ 62 14 TIMING WAVEFORMS ..........................................................................................................................63 15 PACKAGE INFORMATION...................................................................................................................70 16 ORDERING INFORMATION .................................................................................................................70 NOTES ...............................................................................................................................................................71 CONTACT DETAILS.........................................................................................................................................72 DISCLAIMER.....................................................................................................................................................72 Data Sheet Revision 1.3 OX16PCI954 Page 4 ...
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... UART can complete within four PCI clock cycles. Reduces interrupt latency: OX16PCI954 offers shadowed FIFO levels and Interrupt status registers of internal UARTs, and Interrupt Status of internal UARTs and MIO pins to reduce the device driver interrupt latency. OX16PCI954 ...
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... Data Sheet Revision 1.3 Subsystem ID and Subsystem Vendor ID can be set via input pins. Multi-function device: OX16PCI954 is a multi-function device to enable users to load individual device drivers for internal serial ports, the internal parallel port and peripheral devices connected to the Local Bus. Quad Internal OX16C950 UARTs ...
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... XTLI AD31 139 62 GND AD30 140 61 DSR1# AD29 141 60 CTS1# GND 142 59 DTR1# AD28 143 58 RTS1# AD27 144 57 VDD OX16PCI954-TQC60-A AD26 145 56 GND GND 146 55 SOUT1 VDD 147 54 SOUT0 AD25 148 53 RTS0# AD24 149 52 DTR0# C/BE3# 150 51 CTS0# IDSEL 151 ...
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... RS485 transceiver buffer (see register ACR[4:3]) O Tx_Clk_Out[3:0] Transmitter 1x clock (baud rate generator output). For isochronous applications, the 1x (or Nx) transmitter clock may be asserted on the DTR# pins (see register CKS[5:4]) OX16PCI954 Page 8 ...
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... Local bus active-low Data-Strobe (Motorola mode) O LBWR# Local Bus active-low write-strobe (Intel mode) O LBRDWR# Local Bus Read-not-Write control (Motorola mode) O LBRD# Local Bus active-low read-strobe (Intel mode) Z Hi-Z Permanent high impedance (Motorola mode) O LBA[7:0] Local bus address signals LBD[7:0] Local bus data signals OX16PCI954 Page 9 ...
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... Local bus active-low Data-Strobe (Motorola mode) O LBWR# Local Bus active-low write-strobe (Intel mode) O LBRDWR# Local Bus Read-not-Write control (Motorola mode) O LBRD# Local Bus active-low read-strobe (Intel mode) Z Hi-Z Permanent high impedance (Motorola mode) O LBA[12:0] Local bus address signals LBD[31:0] Local bus data signals OX16PCI954 Page 10 ...
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... Power supply. Supplies power to core logic, input buffers and output buffers in steady state G AC GND Supplies GND to output buffers in switching (AC) state G DC GND Ground (0 volts). Supplies GND to core logic, input buffers and output buffers in steady state Table 2: Pin Descriptions OX16PCI954 Page 11 ...
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... Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI, Local Bus and UART pins. Data Sheet Revision 1.3 P_I PCI input P_O PCI output P_I/O PCI bi-directional P_OD PCI open drain G Ground V 5.0V power OX16PCI954 Page 12 ...
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... OXFORD SEMICONDUCTOR LTD & O ONFIGURATION PERATION The OX16PCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 2.2 and PCI Power Management Specification, Revision 1.0. The OX16PCI954 affords maximum configuration flexibility by treating the internal UARTs, Local bus and the parallel port as separate logical functions ...
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... The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OX16PCI954 as a target bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required ...
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... OX16PCI954 Offset 0 Address 00h 04h Revision ID 08h Reserved 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h Cap_Ptr 34h ...
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... A[4:0] are active and the remaining address lines are set to zero. To generate four chip-selects the user should select A3 as the Lower-Address-CS-Decode. In this case A[4:3] will be used internally to decode chip-selects, asserting LBCS0# when the address offset is 00-07h, LBCS1# when OX16PCI954 Parallel port Parallel port base registers Parallel port extended registers Page 16 ...
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... Memory Space: The memory base address registers have an allocated fixed size of 4K bytes in the address space. Since the Local Bus has 8 address lines and the OX16PCI954 only implements DWORD aligned accesses in memory space, the 256 bytes of addressable space per chip select is expanded to 1K ...
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... Power-down filter time. These bits define a value of an internal filter time for power-down interrupt request in power management circuitry in Function0. Once Function0 is ready to go into power down mode, OX16PCI954 will wait for the specified filter time and if Function0 is still in power-down request mode, it can assert a PCI interrupt (see section 6.6). ...
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... MIO6 is an output pin driving ‘1’ 15:14 MIO7 Configuration Register. 00 -> MIO7 is a non-inverting input pin 01 -> MIO7 is an inverting input pin 10 -> MIO7 is an output pin driving ‘0’ 11 -> MIO7 is an output pin driving ‘1’ Data Sheet Revision 1.3 OX16PCI954 Read/Write Reset EEPROM PCI ...
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... Local Bus. These bits are unused in Motorola-type interface. Data Sheet Revision 1.3 Read/Write EEPROM Read/Write EEPROM PCI OX16PCI954 Reset PCI 00h Reset 0h 3h (2h for parallel port) 0h Page 20 ...
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... Only values in the range (0-10 decimal) are valid. Other values are reserved. These parameters apply to both 8-bit and 32-bit Local Bus configurations. See notes in the following page. Data Sheet Revision 1.3 EEPROM OX16PCI954 Read/Write Reset PCI (1h for parallel port) W ...
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... A4 1000 = A12 0001 = A5 1001 = A13 0010 = A6 1010 = A14 0011 = A7 1011 = Res 0100 = A8 1100 = Res 0101 = A9 1101 = Res 0110 = A10 1110 = Res 0111 = A11 1111 = Res 10 = Reserved 11 = Reserved 3 OX16PCI954 Read/Write Reset PCI (2h for parallel port ...
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... The transmitter FIFO level of all internal UARTs are shadowed in Local configuration registers as follows: Bits Description 7:0 UART0 Transmitter FIFO Level (TFL[7:0]) 15:8 UART1 Transmitter FIFO Level (TFL[7:0]) 23:16 UART2 Transmitter FIFO Level (TFL[7:0]) 31:24 UART3 Transmitter FIFO Level (TFL[7:0]) Data Sheet Revision 1.3 OX16PCI954 Read/Write Reset EEPROM PCI - R 0x00h - R 0x00h - ...
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... The location offset of the registers are such that the FIFO levels are usually read before the status registers so that the status of the N characters indicated in the receiver FIFO levels are valid. Data Sheet Revision 1.3 OX16PCI954 Read/Write Reset EEPROM ...
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... GIS register. The MIO Interrupts Mask register bits are all set after a hardware reset to enable the interrupt from all MIO pins from boot up. The default setting for MIO Interrupt Mask bits can be changed using the serial EEPROM. Data Sheet Revision 1.3 Read/Write EEPROM - - OX16PCI954 Reset PCI R 0x0h XXXh ...
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... PCI Interrupts Interrupts in PCI systems are level-sensitive and can be shared. There are sixteen sources of interrupt in the OX16PCI954, one in each UART channel and twelve from Multi-Purpose IO pins (MIO11 to MIO0). The Parallel Port and MIO0 share the same interrupt status bit (GIS[4]). The PCI Power Management power-down interrupt for internal UARTs (Function0) and MIO1 share the status bit GIS[5] ...
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... Data Sheet Revision 1.3 programmed in Power-down Filter Time (LCC[6:5], see section 6.4.1) and if all channels are still inactive, the OX16PCI954 can issue a PCI interrupt enabled. The filter stops the UARTs from issuing too many interrupts whenever the UART activity is intermittent. Upon a power down interrupt, the device driver can change the power- state of Function0 as required ...
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... Function0 power-down is enabled. GIS[5] reflects the state 129 s of the internal power-down mode. MIO1 interrupt is 515 s MIO2 Rising MIO2 Falling X X yes Yes X No OX16PCI954 Operation disabled. Function1 PME_Status Remains unchanged Gets set Remains unchanged Gets set Remains unchanged Page 28 ...
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... OX16C950 UART NTERNAL Each of the four UART channels in the OX16PCI954 operates individually as an OX16C950 high-peformance serial port. Each channel has its own full set of registers, but all share a common clock and FIFOSEL pin. After a device reset, a common configuration state is loaded into all four channels, but after this time each can be operated individually through its own 8-byte block of addressable space ...
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... To program the value to any value from necessary to write this value into the TCR i.e. to set the device cycle sampling clock it would be necessary to write 0x0D to TCR. For further information see section 7.10.3 The UARTs also offer 9-bit data frames for multi-drop industrial applications. OX16PCI954 Page 30 ...
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... Tx Empty Empty Break RI DSR CTS Temporary data storage register and Indexed control register offset value bits Unused Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte) OX16PCI954 Bit 3 Bit 2 Bit 1 Bit 0 Modem Rx Stat THRE RxRDY interrupt interrupt interrupt ...
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... Char Detect Number of characters in the receiver FIFO Number of characters in the transmitter FIFO Data read/written depends on the value written to the SPR prior to the access of this register (see Table 16: 950 Specific Registers OX16PCI954 Bit 2 Bit 1 Bit 0 In-band flow control mode Bit 2 Bit 1 Bit 0 ...
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... SChar 3 SChar 2 0 SIN Modem wakeup Wakeup Wakeup disable Disable FCR[6] FCR[5] FCR[ Table 17: Indexed Control Register Set OX16PCI954 Bit 3 Bit 2 Bit 1 Bit 0 Auto Tx Rx DSR Disable Disable Flow Control Enable 3 Bit “fractional” part of clock prescaler 4 Bit N-times clock ...
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... This command has the same effect on a single channel as a hardware reset except it does not reset the clock source selections (i.e. CKS register). To reset the UART write 0x00 to the Channel Software Reset register ‘CSR’. OX16PCI954 Page 34 ...
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... FCR[4] is unused and FCR[5] defines the FIFO depth as follows: FCR[5]=0: FIFO size is 16 bytes. FCR[5]=1: FIFO size is 128 bytes. In non-Enhanced mode and when FIFOSEL pin is low, FCR[5] is writable only when LCR[7] is set. Note that in Enhanced mode, the FIFO size is increased to 128 bytes when FCR[0] is set. OX16PCI954 Page 35 ...
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... Table 21: LCR Data Length Configuration LCR[2]: Number of stop bits LCR[2] defines the number of stop bits per serial character. LCR[2] Data length 0 5,6,7 6,7,8 Table 22: LCR Stop Bit Number Configuration OX16PCI954 650 FIFO Size 128 112 32 120 112 No ...
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... RHR cleared when the LSR is bit of th read. Note that in 16C550 this bit is only cleared when all of the erroneous data are removed from the FIFO. In 9-bit data framing mode parity is permanently disabled, so this bit is not affected by LSR[2]. OX16PCI954 bit of the received data in RHR. Page 37 ...
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... This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, RTS interrupt is permanently enabled IER[7]: CTS interrupt mask logic 0 Disable the CTS interrupt. logic 1 Enable the CTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, CTS interrupt is permanently enabled. OX16PCI954 Page 38 ...
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... A valid XOFF character is received while in-band flow control is enabled. A received character matches XOFF2 while special character detection is enabled, i.e. EFR[5]=1. A received character matches special character 9-bit mode (see section 7.11.9 cleared on an ISR read of a level 5 interrupt. OX16PCI954 Page 39 ...
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... XON-Any is disabled. logic 1 XON-Any is enabled. In enhanced mode (EFR[4]=1), this bit enables the Xon- Any operation. When Xon-Any is enabled, any received data will be accepted as a valid XON (see in-band flow control, section 7.9.3). OX16PCI954 the Page 40 ...
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... The scratch pad register does not affect operation of the rest of the UART in any way and can be used for temporary data storage. The register may also be used to define an offset value to access the registers in the Indexed Control Register set. For more information on Indexed Control registers see sections 7.2 and 7.11. OX16PCI954 Page 41 ...
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... EFR[4] = 1), where the RTS# pin will be forced inactive high if the RFL reaches the upper flow control threshold. This will be released when the RFL drops below the lower threshold. 650 and 950-mode drivers should use this bit to enable RTS flow control. OX16PCI954 Page 42 ...
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... MCR[1]=1. This allows the software driver to override the automatic flow control and disable the remote transmitter regardless by setting MCR[1]=0 at any time. Automatic DTR/DSR flow control behaves in the same manner as RTS/CTS flow control but is enabled by ACR[3:2], regardless of whether or not the UART is in Enhanced mode. OX16PCI954 Page 43 ...
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... TCR is reset to 0x00 which means that a 16x clock will be used, for compatibility with the 16C550 and compatibles. The maximum baud-rates available for various system clock frequencies at all of the allowable values of TCR are indicated in Table 28 on the following page. These are the OX16PCI954 Page 44 ...
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... OXFORD SEMICONDUCTOR LTD. values in bits-per-second (bps) that are obtained if the divisor latch = 0x01 and the Prescaler is set to 1. The OX16PCI954 has the facility to operate at baud-rates Mbps in normal mode. Table 26 indicates how the value in the register corresponds to the number of clock cycles per bit. TCR[3:0] is used to program the clock. TCR[7:4] are unused and will return “ ...
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... No special character has been detected. logic 1 A special character has been received and is stored in the RHR. This can be used to determine whether a level 5 interrupt was caused by receiving a special character rather than an XOFF. The flag is cleared following the read of the ASR. OX16PCI954 ...
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... FCH are enabled. ACR[6]: ICR read enable logic 0 The Line Status Register is readable. logic 1 The Indexed Control Registers are readable. Setting this bit will map the ICR set to the LSR location for reads. During normal operation this bit should be cleared. OX16PCI954 Page 47 ...
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... Indexed Control Register. Registers ID1, ID2 and ID3 identify the device as an OX16C950 and return 0x16, 0xC9 and 0x50 respectively. The REV register resides at offset 0x0B of ICR and identifies the revision of OX16C950. This register returns 0x01 for revision A of the OX16PCI954. OX16PCI954 Page 48 ...
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... Note however that should an overrun or error interrupt actually occur, an address character may also reside in the FIFO. In this case, the software driver should examine the contents of the receiver FIFO as well as process the error. OX16PCI954 Page 49 ...
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... This read-only register returns the current state of the FCR register (Note that FCR is write-only). This register is included for diagnostic purposes. 7.11.12 Good-data status register ‘GDS’ The GDS register is located at offset 0x10 of the ICR For the definition of Good-data status refer to section 6.4.7. GDS[0]: Good Data Status GDS[7:1]: Reserved OX16PCI954 Page 50 ...
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... If the total number of PCI clock cycles for that frame is greater than 16 clock cycles, OX16PCI954 will post a retry. The master would normally return immediately and complete the operation in the following frame. ...
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... The clock enable bit, when set, enables a copy of the PCI bus clock output on the local bus pin LBCLK. A buffered UART clock can also be asserted on the UART_Clk_Out pin; this means that a single oscillator can be used to drive serial ports on the local bus as well as the internal UARTs. OX16PCI954 Page 52 ...
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... IDIRECTIONAL ARALLEL 9.1 Operation and Mode selection The OX16PCI954 offers a compact, low power, IEEE-1284 (EPP-only) compliant host-interface parallel port, designed to interface to many peripherals such as printers, scanners and external drives. It supports compatibility modes, SPP, NIBBLE and PS2, as well as EPP mode. The register set is compatible with the Microsoft register definition ...
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... DSR[0]: EPP mode: Timeout logic 0 Timeout has not occurred. logic 1 Timeout has occurred (Reading this bit clears it). Other modes: Unused This bit is permanently set to 1. DSR[1]: Unused This bit is permanently set to 1. OX16PCI954 Bit 3 Bit 2 Bit 1 Bit 0 ERR# INT# 1 Timeout ERR# ...
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... These bits define the operational mode of the parallel port. logic ‘000’ SPP logic ‘001’ PS2 logic ‘010’ Reserved logic ‘011’ Reserved logic ‘100’ EPP logic ‘101’ Reserved logic ‘110’ Reserved logic ‘111’ Reserved OX16PCI954 Page 55 ...
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... Local Configuration Register LCC[27:24]. Software can use this register to manipulate the device pins in order to read and modify the EEPROM contents. The OX16PCI954 requires a total of 82 bytes of EEPROM data to program all the EEPROM writable registers. Note that 93C46 and 93C56 EEPROM devices offer 128 and 256 bytes of programmable data respectively ...
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... Lower-Address-CS-Decode. Memory space block size in 32-bit Local Bus. Must be ‘0’. Local Bus clock enable. Bus interface type. UART Interrupt Mask MIO0/Parallel Port interrupt mask Multi-purpose IO interrupt mask. Multi-purpose IO interrupt mask. OX16PCI954 Reference LCC[2] LCC[4:3] LCC[6:5] LCC[7] MIC[7:0] MIC[15:8] MIC[23:16] ...
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... Class Code bits 0x0A 7:0 Class Code bits 0x0B 7:0 Class Code bits 23 to 16. 0x2E 7:0 Subsystem ID bits 0x2F 7:0 Subsystem ID bits 0x3D 7:0 Interrupt pin. 0x42 7:0 Power Management Capabilities bits 0x43 7:0 Power Management Capabilities bits Table 37: EEPROM-writable PCI configuration registers OX16PCI954 Page 58 ...
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... Condition Typical XTAL = 2 MHz XTAL = 15 MHz XTAL = 60 MHz XTAL = 2 MHz XTAL = 15 MHz XTAL = 60 MHz OX16PCI954 Min Max Units -0.3 7 +/- 10 mA -40 125 C Min Max Units 4.5 5 Min Max Units 4 ...
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... V < 0.015 V +4 < V < 25 0.015 CC 0.4V to 2.4V 1 2.4V to 0.4V 1 Table 41: Characteristics of PCI I/O buffers + 2.45) for 3.1 < V OUT OUT ) for 0.71 > V OUT OUT OX16PCI954 Max Unit 5. Eq. A -142 mA Eq ...
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... Data bus floating to LBRD# falling drd t Reference LBCLK to data bus floating at the start of the read zd1 transaction t Reference LBCLK to data bus driven by OX16PCI954 at the end of the zd2 read transaction t Data bus valid to LBRD# rising sd t Data bus valid after LBRD# rising ...
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... Data bus floating to LBDS# falling drd t Reference LBCLK to data bus floating at the start of the read zd1 transaction t Reference LBCLK to data bus driven by OX16PCI954 at the end of the zd2 read transaction t Data bus valid to LBDS# rising sd t Data bus valid after LBDS# rising ...
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... STOP# Figure 4: PCI Read Transaction from internal UARTs CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Figure 5: PCI Write Transaction to internal UARTs Data Sheet Revision 1 Address Data Bus CMD Byte enable Address Data Bus CMD Byte enable# OX16PCI954 5 Page 63 ...
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... Figure 6: PCI Read transaction from Local Configuration registers CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Figure 7: PCI Write transaction to Local Configuration Registers Data Sheet Revision 1 Address Data Bus CMD Byte enable Address Data Bus CMD Byte enable# OX16PCI954 Page 64 ...
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... Figure 8: PCI Read Transaction from Intel-type Local Bus Data Sheet Revision 1 n+5 Where .., 9 Data Byte enable# t ref ard Valid Local Bus Address t zrcs1 t csrd t zrd1 t drd t zd1 Valid Data Valid Data OX16PCI954 n+6 n+7 Data t zrcs2 t rdcs t zrd2 t zd2 Page 65 ...
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... Figure 9: PCI Write Transaction to Intel-type Local Bus Data Sheet Revision 1 n+5 Data Byte enable# t ref awr Valid Local Bus Address t zwcs1 t cswr t zwr1 Valid Local Bus Data t zdv Valid Local Bus Data OX16PCI954 n+6 n+7 Where .., 9 t zwcs2 t wrcs t zwr2 t wrdi t zdf Page 66 ...
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... LBD 2 LBD Figure 10: PCI Read Transaction from Motorola-type Local Bus Data Sheet Revision 1 n+5 Where .., 9 Data Byte enable# t ref ads Valid Local Bus Address t zrds1 t zd1 t drd Valid Data Valid Data OX16PCI954 n+6 n+7 Data t zrds2 t zd2 Page 67 ...
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... Figure 11: PCI Write Transaction to Motorola-type Local Bus Data Sheet Revision 1 n+5 Data Byte enable# t ref ads Valid Local Bus Address t zw1 t wds t zwds1 Valid Local Bus Data t zdv Valid Local Bus Data OX16PCI954 n+6 n+7 Where .., 9 t zw2 t t dsw zwds2 t dsdi t zdf Page 68 ...
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... OXFORD SEMICONDUCTOR LTD IMING AVEFORMS SIN Rx_Clk_In SOUT Tx_Clk_Out Figure 12: Isochronous (x1 clock) timing waveform Data Sheet Revision 1.3 t irs t irh t its OX16PCI954 Page 69 ...
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... OXFORD SEMICONDUCTOR LTD ACKAGE NFORMATION Figure 13: 160 pin Thin Quad Flat Pack (TQFP) package RDERING NFORMATION OX16PCI954-TQC60-A Revision Package Type – 160 TQFP Data Sheet Revision 1.3 OX16PCI954 Page 70 ...
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... OXFORD SEMICONDUCTOR LTD. N OTES Data Sheet Revision 1.3 This page has been intentionally left blank OX16PCI954 Page 71 ...
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... No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of Oxford Semiconductor Ltd. Oxford Semiconductor’s terms and conditions of sale apply at all times. Data Sheet Revision 1.3 OX16PCI954 Page 72 ...