ISP1507BBS ST-Ericsson Inc, ISP1507BBS Datasheet - Page 23
![IC, TRANSCEIVER, USB OTG, 32HVQFN](/photos/19/0/190010/42557130_sml.jpg)
ISP1507BBS
Manufacturer Part Number
ISP1507BBS
Description
IC, TRANSCEIVER, USB OTG, 32HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1507BBS.pdf
(81 pages)
Specifications of ISP1507BBS
Usb Type
USB Transceiver
Usb Version
2.0
Data Rate
12Mbps
No. Of Ports
1
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1507BBSTM
Manufacturer:
SEMIKRON
Quantity:
22
CD00222689
Product data sheet
Fig 6.
DATA[7:0]
REG1V8
REG1V8
V
detector
internal
CLOCK
internal
CC(I/O)
XTAL1
POR
V
NXT
STP
DIR
CC
t1 = V
t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive
either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during t
t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level.
DIR is driven to HIGH and the other pins are driven to LOW.
t4 = The ISP1507 regulator is powered up and is stable.
t5 = The internal PLL is stabilized after t
be stabilized after t
The DIR pin will remain LOW before the link issues a RESET command to the ISP1507.
t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.
Power-up and reset sequence required before the ULPI bus is ready for use
CC
9.3.1 Interface protection
and V
CC(I/O)
t1
By default, the ISP1507 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1507 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
startup(PLL)
are applied to the ISP1507. The ISP1507 regulator starts to turn on.
t2
t
REGUP
from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.
t3
startup(PLL)
t4
t
startup(PLL)
Rev. 04 — 20 May 2010
. If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will
t5
internal clocks stable
RESET command
TXCMD
D
ISP1507A; ISP1507B
internal reset
ULPI HS USB OTG transceiver
REGUP
.
© ST-ERICSSON 2010. All rights reserved.
RXCMD
update
004aaa885
bus idle
t6
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