5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 21

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5M240ZT100C5N

Manufacturer Part Number
5M240ZT100C5N
Description
IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
Manufacturer
Altera
Series
MAX Vr

Specifications of 5M240ZT100C5N

Cpld Type
FLASH
No. Of Macrocells
192
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Rohs Compliant
Yes
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
240
Number Of Macrocells
192
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device
Table 3–30. Global Clock External I/O Timing Parameters for the 5M1270Z Device
Table 3–31. Global Clock External I/O Timing Parameters for the 5M2210Z Device
January 2011 Altera Corporation
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Not applicable to the F324 package of the 5M1270Z device.
t
t
t
t
t
t
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Only applicable to the F324 package of the 5M1270Z device.
t
t
t
t
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
PD1
PD2
SU
H
Symbol
Symbol
Symbol
clock input pin maximum frequency.
clock input pin maximum frequency.
Table
Table
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
3–29:
3–30:
Table 3–30
5M1270Z device.
Table 3–31
Parameter
Parameter
Parameter
lists the external I/O timing parameters for the F324 package of the
lists the external I/O timing parameters for the 5M2210Z device.
Condition
Condition
Condition
10 pF
10 pF
10 pF
10 pF
10 pF
Min
216
Min
216
Min
216
2.0
4.0
1.5
4.0
1.5
0
0
C4
C4
C4
(Note
(Note
(Note 1)
247.5
247.5
Max
Max
Max
9.1
4.8
6.0
9.1
4.8
1),
1),
(Part 1 of 2)
(2)
(2)
Min
Min
Min
266
266
266
5.0
1.9
2.0
5.0
1.9
(Part 2 of 2)
0
0
C5, I5
C5, I5
C5, I5
MAX V Device Handbook
201.1
201.1
Max
Max
11.2
Max
11.2
5.9
7.4
5.9
MHz
MHz
Unit
Unit
Unit
3–21
ps
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns

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