EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 24

IC PLD EEPROM 160 MACROCELL 10NS QFP-160

EPM7160SQC160-10N

Manufacturer Part Number
EPM7160SQC160-10N
Description
IC PLD EEPROM 160 MACROCELL 10NS QFP-160
Manufacturer
Altera
Series
MAX 7000Sr
Datasheet

Specifications of EPM7160SQC160-10N

Cpld Type
EEPROM
No. Of Macrocells
160
No. Of I/o's
104
Propagation Delay
10ns
Global Clock Setup Time
3.4ns
Frequency
149.3MHz
Supply Voltage Range
4.75V To 5.25V
Family Name
MAX 7000S
Memory Type
EEPROM
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
10
# I/os (max)
104
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7160SQC160-10N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM7160SQC160-10N
Manufacturer:
ALTERA
0
MAX 7000 Programmable Logic Device Family Data Sheet
24
f
Figure 9
Figure 9. MAX 7000 JTAG Waveforms
Table 12
devices.
For more information, see
Boundary-Scan Testing in Altera
Captured
Symbol
Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
t
t
t
t
t
t
t
t
t
t
t
t
t
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
shows the timing requirements for the JTAG signals.
shows the JTAG timing parameters and values for MAX 7000S
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
Application Note 39 (IEEE 1149.1 (JTAG)
t
Devices).
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Altera Corporation
100
Min
50
50
20
45
20
45
t
Max
JPXZ
25
25
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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