EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 34

IC PLD EEPROM 160 MACROCELL 10NS QFP-160

EPM7160SQC160-10N

Manufacturer Part Number
EPM7160SQC160-10N
Description
IC PLD EEPROM 160 MACROCELL 10NS QFP-160
Manufacturer
Altera
Series
MAX 7000Sr
Datasheet

Specifications of EPM7160SQC160-10N

Cpld Type
EEPROM
No. Of Macrocells
160
No. Of I/o's
104
Propagation Delay
10ns
Global Clock Setup Time
3.4ns
Frequency
149.3MHz
Supply Voltage Range
4.75V To 5.25V
Family Name
MAX 7000S
Memory Type
EEPROM
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
10
# I/os (max)
104
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7160SQC160-10N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM7160SQC160-10N
Manufacturer:
ALTERA
0
MAX 7000 Programmable Logic Device Family Data Sheet
34
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = on
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
Parameter
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(2)
(2)
(8)
C1 = 5 pF
Conditions
(7)
(2)
(7)
(2)
MAX 7000E (-10P) MAX 7000 (-10)
Min
2.0
3.0
3.0
0.5
Note (1)
11.0
Max
Speed Grade
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
MAX 7000E (-10)
Min
3.0
3.0
3.0
0.5
Altera Corporation
11.0
Max
1.0
1.0
5.0
1.0
1.0
1.0
5.0
0.8
5.0
5.0
2.0
2.0
2.5
6.0
5.0
5.5
9.0
5.0
5.0
1.0
3.0
3.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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