EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 64

• Manufacturer Part Number: EPM7160SQC160-10N
• Description: IC PLD EEPROM 160 MACROCELL 10NS QFP-160
• Manufacturer: Altera
• Series: MAX 7000Sr

Specifications of EPM7160SQC160-10N

• Cpld Type: EEPROM
• No. Of Macrocells: 160
• No. Of I/o's: 104
• Propagation Delay: 10ns
• Global Clock Setup Time: 3.4ns
• Frequency: 149.3MHz
• Supply Voltage Range: 4.75V To 5.25V
• Family Name: MAX 7000S
• Memory Type: EEPROM
• # Macrocells: 160
• Number Of Usable Gates: 3200
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 10
• # I/os (max): 104
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX 7000 Programmable Logic Device Family Data Sheet
Revision
History
64
The information contained in the MAX 7000 Programmable Logic Device
Family Data Sheet version 6.7 supersedes information published in
previous versions. The following changes were made in the MAX 7000
Programmable Logic Device Family Data Sheet version 6.7:
Version 6.7
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.7:
■
Version 6.6
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.6:
■
■
Version 6.5
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.5:
■
Version 6.4
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.4:
■
Version 6.3
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.3:
■
Reference to AN 88: Using the Jam Language for ISP & ICR via an
Embedded Processor has been replaced by AN 122: Using Jam STAPL for
ISP & ICR via an Embedded Processor.
Added
Added
“Programming Times” section on page 18.
Updated text on
Added
Updated the
Only)” section on page
Tables 6
“Programming Sequence” section on page 17
Note (5)
“Open-Drain Output Option (MAX 7000S Devices
through 8.
on
page
page
16.
20.
28.
Altera Corporation
and