M4A5-192/96-10VNC LATTICE SEMICONDUCTOR, M4A5-192/96-10VNC Datasheet - Page 20

• Manufacturer Part Number: M4A5-192/96-10VNC
• Description: MACH4 ISP EEPLD, SMD, TQFP144, 5V
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspMACH 4Ar

Specifications of M4A5-192/96-10VNC

• No. Of Macrocells: 192
• No. Of I/o's: 96
• Propagation Delay: 10ns
• Frequency: 100MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Logic Case: RoHS Compliant

ispMACH 4A TIMING MODEL
The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a
ispMACH 4A device, and at the same time, be easy to understand. This model accurately
describes all combinatorial and registered paths through the device, making a distinction
between internal feedback and external feedback. A signal uses internal feedback when it is fed
back into the switch matrix or block without having to go through the output buffer. The input
register specifications are also reported as internal feedback. When a signal is fed back into the
switch matrix after having gone through the output buffer, it is using external feedback.
The parameter, t
to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter
designator is followed by an “i”. By adding t
is derived. For example, t
timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and
High Speed Design for a more detailed discussion about the timing parameters.
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual
macrocell with the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is
independent of the logic required by the design. Other competitive CPLDs incur serious timing
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and
SpeedLocking combine to give designs easy access to the performance required in today’s
designs.
20
BLK CLK
IN
BUF
t
t
t
t
t
t
t
t
SIRS
HIRS
SIL
HIL
SIRZ
HIRZ
SILZ
HILZ
INPUT LATCH
INPUT REG/
, is defined as the time it takes to go from feedback through the output buffer
t
t
t
t
PDILi
ICOSi
IGOSi
PDILZi
PD
Q
= t
Central
Switch
Matrix
PDi
Figure 15. ispMACH 4A Timing Model
+ t
BUF
ispMACH 4A Family
t
. A diagram representing the modularized ispMACH 4A
PL
(External Feedback)
(Internal Feedback)
BUF
to this internal parameter, the external parameter
COMB/DFF/TFF/
t
t
t
t
t
t
LATCH/SR*/JK*
SS(T)
SA(T)
H(S/A)
S(S/A)L
H(S/A)L
SRR
*emulated
S/R
t
t
t
t
t
PDi
PDLi
CO(S/A)i
GO(S/A)i
SRi
Q
t
BUF
t
t
ER
EA
t
SLW
17466G-025
OUT