M52S128168A-7.5TG ELITE SEMICONDUCTOR, M52S128168A-7.5TG Datasheet - Page 15

• Manufacturer Part Number: M52S128168A-7.5TG
• Description: IC, SDRAM, 128MBIT, 133MHZ, TSOP-54
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5TG

• Memory Type: DRAM - Sychronous
• Memory Configuration: 2M X 16
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Frequency: 133MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Page Size: 128MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
COMMANDS
Mode register set command
command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
(t
Extended Mode register set command
Activate command
address selected by A0 through A11.
Elite Semiconductor Memory Technology Inc.
MRD
The DRAM has a mode register that defines how the device operates. In this
The mode register can be set only when all banks are in idle state. During 2CLK
The DRAM has a extended mode register that defines how to set PASR, DS.
The DRAM has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
This command corresponds to a conventional DRAM’s RAS falling.
) following this command, the DRAM cannot accept any other commands.
(
( CS , RAS , CAS , WE , BA0 = Low ; BA1= High)
( CS , RAS = Low, CAS , WE = High)
CS
,
RAS
,
CAS
,
WE
,
BA1, BA0 = Low)
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
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