M52S128168A-7.5TG ELITE SEMICONDUCTOR, M52S128168A-7.5TG Datasheet - Page 16

• Manufacturer Part Number: M52S128168A-7.5TG
• Description: IC, SDRAM, 128MBIT, 133MHZ, TSOP-54
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5TG

• Memory Type: DRAM - Sychronous
• Memory Configuration: 2M X 16
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Frequency: 133MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Page Size: 128MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
Precharge command
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
precharging bank during t
This command corresponds to a conventional DRAM’s RAS rising.
Write command
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
This command sets the burst start address given by the column address.
Elite Semiconductor Memory Technology Inc.
This command begins precharge operation of the bank selected by BA1 and BA0
After this command, the DRAM can’t accept the activate command to the
If the mode register is in the burst write mode, this command sets the burst start
Read data is available after CAS latency requirements have been met.
( CS , RAS , WE = Low, CAS = High )
( CS , CAS , WE = Low, RAS = High)
( CS , CAS = Low, RAS , WE = High)
RP
(precharge to activate command period).
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
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