M52S128168A-7.5TG ELITE SEMICONDUCTOR, M52S128168A-7.5TG Datasheet - Page 34

IC, SDRAM, 128MBIT, 133MHZ, TSOP-54

M52S128168A-7.5TG

Manufacturer Part Number
M52S128168A-7.5TG
Description
IC, SDRAM, 128MBIT, 133MHZ, TSOP-54
Manufacturer
ELITE SEMICONDUCTOR
Datasheet

Specifications of M52S128168A-7.5TG

Memory Type
DRAM - Sychronous
Memory Configuration
2M X 16
Ic Interface Type
Parallel
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Frequency
133MHz
Filter Terminals
SMD
Rohs Compliant
Yes
Page Size
128MB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ESMT
Page Read & Write Cycle at Same Bank @ Burst Length = 4
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid
Elite Semiconductor Memory Technology Inc.
2. Row precharge will interrupt writing. Last data input , t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
bus contention.
end of burst. Input data after Row precharge cycle will be masked internally.
RDL
before row precharge , will be written.
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
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