LPC2103FBD48-S NXP Semiconductors, LPC2103FBD48-S Datasheet - Page 14

• Manufacturer Part Number: LPC2103FBD48-S
• Description: IC, 32BIT MCU, ARM7, 75MHZ, LQFP-48
• Manufacturer: NXP Semiconductors

Specifications of LPC2103FBD48-S

• Controller Family/series: (ARM7)
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 70MHz
• No. Of Timers: 6
• Digital Ic Case Style: LQFP
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.10.1 Features
6.11.1 Features
6.10 I
6.11 SPI serial I/O controller
The LPC2101/02/03 each contain two I
The I
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the
capability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
it can be controlled by more than one bus master connected to it.
The I
I
The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.
2
2
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C-bus).
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•
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•
•
•
•
•
•
•
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C-bus serial I/O controllers
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
Compliant with standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast
2
C-bus can also be used for test and diagnostic purposes.
Rev. 04 — 2 June 2009
2
C-bus interface.
2
C-bus controllers.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
2
C-bus is a multi-master bus,
© NXP B.V. 2009. All rights reserved.
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