LPC2103FBD48-S NXP Semiconductors, LPC2103FBD48-S Datasheet - Page 15

• Manufacturer Part Number: LPC2103FBD48-S
• Description: IC, 32BIT MCU, ARM7, 75MHZ, LQFP-48
• Manufacturer: NXP Semiconductors

Specifications of LPC2103FBD48-S

• Controller Family/series: (ARM7)
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 70MHz
• No. Of Timers: 6
• Digital Ic Case Style: LQFP
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.12.1 Features
6.13.1 Features
6.12 SSP serial I/O controller
6.13 General purpose 32-bit timers/external event counters
The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. However, only a single master and a single slave can communicate on the bus during
a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to
16 bits flowing from the master to the slave and from the slave to the master. Often only
one of these data streams carries meaningful data.
The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2101/02/03 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer than a period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
•
•
•
•
•
•
•
•
•
•
•
•
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor’s Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
Four bits to 16 bits per frame
A 32-bit timer/counter with a programmable 32-bit prescaler.
External event counter or timer operation.
Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
– Set LOW on match.
Rev. 04 — 2 June 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
15 of 37