LPC2103FBD48-S NXP Semiconductors, LPC2103FBD48-S Datasheet - Page 21
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
LPC2103FBD48-S
Manufacturer Part Number
LPC2103FBD48-S
Description
IC, 32BIT MCU, ARM7, 75MHZ, LQFP-48
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2102FHN48551.pdf
(37 pages)
Specifications of LPC2103FBD48-S
Controller Family/series
(ARM7)
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
70MHz
No. Of Timers
6
Digital Ic Case Style
LQFP
Core Size
32 Bit
Program Memory Size
32KB
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.18.1 EmbeddedICE
6.18.2 RealMonitor
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the
remote debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a debug communication channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
coprocessor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock
(TCK) must be slower than
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2101/02/03 contain a specific configuration of
RealMonitor software programmed into the on-chip boot ROM memory.
Rev. 04 — 2 June 2009
1
6
of the CPU clock (CCLK) for the JTAG interface to operate.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
21 of 37