PIC16F1827-I/ML Microchip Technology, PIC16F1827-I/ML Datasheet - Page 179
![IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F1827-I/ML
Manufacturer Part Number
PIC16F1827-I/ML
Description
IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1827-I/ML
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 179 of 400
- Download datasheet (7Mb)
20.3
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
20.4
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will
continue to run during Sleep.
20.5
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 20.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
20.5.1
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
© 2009 Microchip Technology Inc.
Note:
Note:
Timer1 Prescaler
Timer1 Oscillator
Timer1 Operation in
Asynchronous Counter Mode
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Preliminary
20.6
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 Gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 Gate can also be driven by multiple selectable
sources.
20.6.1
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 20-3 for timing details.
TABLE 20-3:
20.6.2
The Timer1 Gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 20-4:
T1GSS
T1CLK
00
01
10
11
↑
↑
↑
↑
PIC16F/LF1826/27
Timer1 Gate
Timer1 Gate Pin
Overflow of Timer0
(TMR0 increments from FFh to 00h)
Comparator 1 Output SYNCC1OUT
(optionally synchronized out)
Comparator 2 Output SYNCC2OUT
(optionally synchronized out)
T1GPOL
TIMER1 GATE ENABLE
TIMER1 GATE SOURCE
SELECTION
0
0
1
1
TIMER1 GATE ENABLE
SELECTIONS
TIMER1 GATE SOURCES
Timer1 Gate Source
T1G
0
1
0
1
Counts
Holds Count
Holds Count
Counts
Timer1 Operation
DS41391B-page 179
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