PIC16F1827-I/ML Microchip Technology, PIC16F1827-I/ML Datasheet - Page 311
![IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F1827-I/ML
Manufacturer Part Number
PIC16F1827-I/ML
Description
IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1827-I/ML
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 311 of 400
- Download datasheet (7Mb)
FIGURE 25-12:
TABLE 25-8:
© 2009 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISB
TXSTA
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
CREN bit
SREN bit
bit SREN
RCIF bit
RCREG
Name
RX/DT
Write to
Read
pin
*
Page provides register information.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
EUSART Receive Data Register
Baud Rate Generator Data Register Low
Baud Rate Generator Data Register High
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
CSRC
SPEN
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
GIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TRISB6
bit 0
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
bit 1
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
bit 2
TRISB4
Preliminary
CREN
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
bit 3
SSP1IE
SSP1IF
ADDEN
TRISB3
SENDB
BRG16
IOCIE
Bit 3
bit 4
PIC16F/LF1826/27
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
Bit 1
INTF
bit 6
TMR1IE
TMR1IF
ABDEN
TRISB0
bit 7
IOCIF
RX9D
TX9D
Bit 0
DS41391B-page 311
Register
on Page
292*
299*
299*
298
297
126
296
89
90
94
‘0’
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