LPC2220FBD144 NXP Semiconductors, LPC2220FBD144 Datasheet - Page 27

• Manufacturer Part Number: LPC2220FBD144
• Description: IC, 16/32BIT ARM7 MCU, 64K RAM, SMD
• Manufacturer: NXP Semiconductors

Specifications of LPC2220FBD144

• No. Of I/o's: 76
• Ram Memory Size: 64KB
• Cpu Speed: 75MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Core Size: 32bit
• Oscillator Type: External Only
• Controller Family/series: LPC22xx
• Peripherals: ADC, RTC
• Rohs Compliant: Yes

NXP Semiconductors
LPC2210_2220_6
Product data sheet
6.17.1 Features
6.18.1 Features
6.17 Watchdog timer
6.18 Real-time clock
6.19 Pulse width modulator
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).
The PWM is based on the standard timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2210/2220. The timer is designed to count
cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other
actions when specified timer values occur, based on seven match registers. The PWM
function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
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Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (T
T
Measures the passage of time to maintain a calendar and clock.
Ultra-low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
Programmable reference clock divider allows adjustment of the RTC to match various
crystal frequencies.
cy(PCLK)
4.
Rev. 06 — 11 December 2008
cy(PCLK)
256
4) to (T
16/32-bit ARM microcontrollers
cy(PCLK)
LPC2210/2220
2
32
© NXP B.V. 2008. All rights reserved.
4) in multiples of
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