UPD78F1154GK-GAK-AX NEC, UPD78F1154GK-GAK-AX Datasheet - Page 61

16BIT MCU, 128K FLASH, 8K RAM, SMD

UPD78F1154GK-GAK-AX

Manufacturer Part Number
UPD78F1154GK-GAK-AX
Description
16BIT MCU, 128K FLASH, 8K RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F1154GK-GAK-AX

Controller Family/series
UPD78F
No. Of I/o's
70
Ram Memory Size
8192Byte
Cpu Speed
20MHz
No. Of Timers
9
No. Of
RoHS Compliant
Core Size
16bit
Program Memory Size
128KB
Oscillator Type
External, Internal

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1154GK-GAK-AX
Manufacturer:
NEC
Quantity:
100
8. INTERRUPT FUNCTION
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
Maskable
Interrupt
A total of 42 interrupt sources are provided, divided into the following two types.
Type
• Maskable interrupt: 41
• Software interrupt: 1
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 8-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
simultaneously. Zero indicates the highest priority and 40 indicates the lowest priority.
Priority
Default
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
Note 1
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTST3
INTSR3
INTSRE3
INTDMA0
INTDMA1
INTST0
/INTCSI00
INTSR0
/INTCSI01
INTSRE0
INTST1
/INTCSI10
/INTIIC10
INTSR1
INTSRE1
INTIIC0
Name
Table 8-1. Interrupt Source List (1/3)
Preliminary Product Information U17892EJ2V0PM
Watchdog timer interval
(75% of overflow time)
Low-voltage detection
Pin input edge detection
End of UART3 transmission
End of UART3 reception
UART3 communication error occurrence
End of DMA0 transfer
End of DMA1 transfer
End of UART0 transmission/end of CSI00
communication
End of UART0 reception/end of CSI01
communication
CSI00/CSI01/UART0 communication error
occurrence
End of UART1 transmission/end of CSI10
communication/end of IIC10 communication
End of UART1 reception
CSI10/UART1/IIC10 communication error
occurrence
End of IIC0 communication
Interrupt Source
Trigger
Note 4
Note 3
Internal
External
Internal
Internal/
External
Address
000AH
000CH
000EH
001AH
001CH
001EH
002AH
Vector
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0020H
0022H
0024H
0026H
0028H
Table
78K0R/KF3
Configuration
Type
Basic
(A)
(B)
(A)
Note 2
61

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