PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 39

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.0
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.
4.1
The
PIC24FJ256GB110 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 4-1:
 2009 Microchip Technology Inc.
Note:
program
Device Config Registers
Alternate Vector Table
PIC24FJ64GB1XX
Interrupt Vector Table
Flash Config Words
MEMORY ORGANIZATION
Program Address Space
Program Memory
(22K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Memory areas are not shown to scale.
Read ‘0’
address
PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES
memory
Device Config Registers
PIC24FJ128GB1XX
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
Program Memory
(44K instructions)
GOTO Instruction
Unimplemented
Reset Address
space
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
of
PIC24FJ256GB110 FAMILY
the
Device Config Registers
PIC24FJ192GB1XX
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
Program Memory
(67K instructions)
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ256GB110 family of
devices are shown in Figure 4-1.
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
Device Config Registers
PIC24FJ256GB1XX
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
Program Memory
(87K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
DS39897C-page 39
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
00ABFEh
00AC00h
0157FEh
015800h
020BFEh
020C00h
02ABFEh
02AC00h
7FFFFFh
800000h
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
FFFFFFh