CS4362-KQZ Cirrus Logic Inc, CS4362-KQZ Datasheet - Page 18

• Manufacturer Part Number: CS4362-KQZ
• Description: IC,Audio Processor,QFP,48PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4362-KQZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 6
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 390mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1644

18
4.2.2
4.3
4.3.1
DIF2
SZC1
0
0
0
0
1
1
1
1
7
1
Mode Control 3 (address 03h)
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital Interface Format pins. An additional write of 99h
to register 00h and 80h to register 1Ah is required to access the modes denoted with *.
Serial Audio Data Clock Source (SDINXCLK)
Default = 0
0 - SDINx clocked by SCLK1 and LRCK1
1 - SDINx clocked by SCLK2 and LRCK2
Function:
The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given SDINx
line. For more details see
Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a tim-
eout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
DIF1
0
0
1
1
0
0
1
1
SZC0
6
0
DIFO
0
1
0
1
0
1
0
1
SNGLVOL
Table 2. Digital Interface Formats - DSD Mode
5
0
“Clock Source Selection” on page
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
RMP_UP
4
0
Reserved
DESCRIPTION
3
0
29.
AMUTE
2
1
MUTEC1
1
0
CS4362
MUTEC0
DS257F2
Note
0
0
*
*
*
*
*
*