AD7143ACPZ Analog Devices Inc, AD7143ACPZ Datasheet - Page 28

• Manufacturer Part Number: AD7143ACPZ
• Description: IC, CDC, 16BIT, SMD, LFCSP-16, 7143
• Manufacturer: Analog Devices Inc

Specifications of AD7143ACPZ

• Supply Voltage Range: 2.6V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 16
• Svhc: No SVHC (18-Jun-2010)
• Package / Case: LFCSP
• Base Number: 7143
• Ic Function: Programmable Controller For Capacitance Touch Sensors
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7143
SERIAL INTERFACE
The AD7143 is available with a fixed address I
interface.
I
The AD7143 supports the industry standard 2-wire I
interface protocol. The two wires associated with the I
the SCLK and the SDA inputs. The SDA is an I/O pin that allows
both register write and register readback operations. The AD7143 is
always a slave device on the I
The AD7143 has a single fixed 7-bit device address,
Address 0101 110. The AD7143 responds when the master
device sends its device address over the bus. The AD7143
cannot initiate data transfers on the bus.
Table 14. AD7143 I
DEV
A6
0
Data Transfer
Data is transferred over the I
The master initiates a data transfer by establishing a start con-
dition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCLK, remains high. This
indicates that an address/data stream follows.
2
C COMPATIBLE INTERFACE
SCLK
SDA
START
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0].
4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
DEV
A5
1
ACK
27
D15
t
1
28
DEV
A4
0
DEV
A6
REGISTER DATA [D15:D8]
2
D14
C Fixed Device Address
1
29
DEV
A5
AD7143 DEVICE ADDRESS
2
2
C serial interface bus.
DEV
A3
1
2
DEV
C serial interface in 8-bit bytes.
A4
3
DEV
A3
t
2
D9
4
34
DEV
A2
1
DEV
A2
D8
Figure 39. Example of I
t
5
4
35
DEV
A1
ACK
2
6
C-compatible
t
36
3
DEV
A1
1
DEV
A0
2
D7
C serial
2
7
C timing are
37
R/W
REGISTER DATA [D7:D0]
D6
8
38
t
DEV
A0
0
5
ACK
2
C Timing for Single Register Write Operation
Rev. 0 | Page 28 of 56
9
A15
10
REGISTER ADDRESS [A15:A8]
A14
D1
11
43
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/ W bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus now remain idle
while the selected device waits for data to be read from, or
written to it. If the R/ W bit is a 0, the master writes to the slave
device. If the R/ W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period, since a low-to-high transition when the clock is
high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCLK remains high. If the AD7143
encounters a stop condition, it returns to its idle condition, and
the address pointer register resets to Address 0x00.
D0
44
ACK
45
A9
16
46
STOP
t
6
A8
17
ACK
t
18
8
A7
START
19
t
REGISTER ADDRESS [A7:A0]
7
A6
20
DEV
AD7143 DEVICE ADDRESS
A6
1
DEV
A5
A1
2
25
DEV
A4
A0
3
26