FM6124-QG Ramtron, FM6124-QG Datasheet - Page 5

• Manufacturer Part Number: FM6124-QG
• Description: FRAM, 24KB, EVENT DATA REC, QFP44
• Manufacturer: Ramtron

Specifications of FM6124-QG

• Memory Size: 24KB
• Nvram Features: RTC
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Package / Case: QFP
• Interface: I2C
• Memory: RoHS Compliant
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes
• Access Time: 100 KBPs
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

Slave Address
The first byte that the FM6124 expects after a Start
condition is the slave address. As shown in figures
below, the slave address contains the Slave ID,
Device Select address, and a bit that specifies if the
transaction is a read or a write.
The FM6124 has two Slave Addresses (Slave IDs)
associated with two logical devices. To access the
memory device, bits 7-4 should be set to 1010b. The
other logical device within the FM6124 is the Event
Recorder configuration and data access, the real-time
clock and MCU companion. To access this device,
bits 7-4 of the slave address should be set to 1101b.
A bus transaction with this slave address will not
affect the memory in any way. The figures below
illustrate the two Slave Addresses.
The Device Select bits allow multiple devices of the
same type to reside on the 2-wire bus. The device
select bits (bits 2-1) select one of four parts on a two-
wire bus. They must match the corresponding value
on the external address pins in order to select the
device. Bit 0 is the read/write bit. A “1” indicates a
read operation, and a “0” indicates a write operation.
Addressing Overview – Memory
After the FM6124 acknowledges the Slave Address,
the master can place the memory address on the bus
for a write operation. The address requires two bytes.
The first is the MSB (upper byte). Following the
MSB is the LSB (lower byte) which contains the
remaining eight address bits. The address is latched
internally. Each access causes the latched address to
be incremented automatically. The current address is
the value that is held in the latch, either a newly
Rev. 4.0 (EOL)
July 2010
7
7
1
1
F
IGURE
Slave ID
Slave ID
0
1
6
6
F
IGURE
4. S
5
5
1
0
LAVE
3. S
LAVE
4
4
0
1
A
DDRESS
A
DDRESS
3
3
X
X
– EDR/C
A1
A1
2
2
- M
Device
Device
Select
Select
EMORY
OMPANION
A0
A0
1
1
R/W
R/W
0
0
written value or the address following the last access.
The current address will be held as long as VDD >
VTP or until a new value is written. Accesses to the
clock do not affect the current memory address.
Reads always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
After transmission of each data byte, just prior to the
Acknowledge, the FM6124 increments the internal
address. This allows the next sequential byte to be
accessed with no additional addressing externally.
After the last address is reached, the address latch
will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Addressing Overview – EDR, RTC & Companion
The
Companion operate in a similar manner to the
memory, except that it uses only one byte of address.
Addresses 00h to 33h corresponds to special function
registers. Attempting to load addresses above 33h is
an illegal condition; the FM6124 will return a
NACK and abort the 2-wire transaction.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM6124 begins. For a read, the FM6124 will place 8
data bits on the bus then wait for an ACK from the
master. If the ACK occurs, the FM6124 will transfer
the next byte. If the ACK is not sent, the FM6124
will end the read operation. For a write operation, the
FM6124 will accept 8 data bits from the master then
send an Acknowledge. All data transfer occurs MSB
(most significant bit) first.
Memory Write Operation
All memory writes begin with a Slave Address, then
a memory address. The bus master indicates a write
operation by setting the slave address LSB to a 0.
After addressing, the bus master sends each byte of
data to the memory and the memory generates an
Acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
to 0000h. Internally, the actual memory write occurs
after the 8
before the Acknowledge is sent. Therefore, if the
user desires to abort a write without altering the
memory contents, this should be done using a Start
or Stop condition prior to the 8
that follow illustrate a single- and multiple-writes to
memory.
Event
th
data bit is transferred. It will be complete
Recorder,
RTC,
th
data bit. The figures
and
Processor
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