LFXP2-17E-5QN208C8W LATTICE SEMICONDUCTOR, LFXP2-17E-5QN208C8W Datasheet - Page 11

• Manufacturer Part Number: LFXP2-17E-5QN208C8W
• Description: FPGA, 17K LUTS, 146 IO, DSP, 208PQFP
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeXP2r

Specifications of LFXP2-17E-5QN208C8W

• No. Of Macrocells: 8500
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• No. Of I/o's: 146
• Clock Management: PLL
• Core Supply Voltage Range: 1.14V To 1.26V
• I/o Supply: RoHS Compliant

Lattice Semiconductor
Figure 2-5. Clock Divider Connections
Clock Distribution Network
LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based sec-
ondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to sup-
port high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock
inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs
and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There
are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources.
CLKOP (GPLL)
ECLK
RELEASE
RST
2-8
CLKDIV
LatticeXP2 Family Data Sheet
÷1
÷2
÷4
÷8
Architecture