LFXP2-17E-5QN208C8W LATTICE SEMICONDUCTOR, LFXP2-17E-5QN208C8W Datasheet - Page 58
LFXP2-17E-5QN208C8W
Manufacturer Part Number
LFXP2-17E-5QN208C8W
Description
FPGA, 17K LUTS, 146 IO, DSP, 208PQFP
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet
1.LFXP2-5E-5TN144C.pdf
(93 pages)
Specifications of LFXP2-17E-5QN208C8W
No. Of Macrocells
8500
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
146
Clock Management
PLL
Core Supply Voltage Range
1.14V To 1.26V
I/o Supply
RoHS Compliant
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Lattice Semiconductor
Typical Building Block Function Performance
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Register-to-Register Performance
Basic Functions
16-bit Decoder
32-bit Decoder
64-bit Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Basic Functions
16-bit Decoder
32-bit Decoder
64-bit Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
8-bit Adder
16-bit Adder
64-bit Adder
16-bit Counter
32-bit Counter
64-bit Counter
64-bit Accumulator
Embedded Memory Functions
512x36 Single Port RAM, EBR Output Registers
1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers)
1024x18 True-Dual Port RAM (Read-Before-Write, EBR Output Registers)
1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers)
Distributed Memory Functions
16x4 Pseudo-Dual Port RAM (One PFU)
32x2 Pseudo-Dual Port RAM
64x1 Pseudo-Dual Port RAM
DSP Functions
18x18 Multiplier (All Registers)
9x9 Multiplier (All Registers)
36x36 Multiply (All Registers)
18x18 Multiply/Accumulate (Input and Output Registers)
18x18 Multiply-Add/Sub-Sum (All Registers)
Function
Function
3-14
1
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
-7 Timing
-7 Timing
521
537
484
744
678
616
529
570
507
293
541
440
321
261
315
315
225
231
760
455
351
365
365
323
281
305
4.4
5.2
5.6
3.7
3.9
4.3
4.5
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
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