LFXP2-17E-5QN208C8W LATTICE SEMICONDUCTOR, LFXP2-17E-5QN208C8W Datasheet - Page 17
![FPGA, 17K LUTS, 146 IO, DSP, 208PQFP](/photos/19/4/190400/ge208pqfp05-40_sml.jpg)
LFXP2-17E-5QN208C8W
Manufacturer Part Number
LFXP2-17E-5QN208C8W
Description
FPGA, 17K LUTS, 146 IO, DSP, 208PQFP
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet
1.LFXP2-5E-5TN144C.pdf
(93 pages)
Specifications of LFXP2-17E-5QN208C8W
No. Of Macrocells
8500
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
146
Clock Management
PLL
Core Supply Voltage Range
1.14V To 1.26V
I/o Supply
RoHS Compliant
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Lattice Semiconductor
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice0 through Slice2 Clock Selection
Figure 2-14. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Secondary Clock
Secondary Clock
Primary Clock
Routing
Routing
Vcc
Vcc
12
12
8
4
1
3
1
2-14
25:1
16:1
Clock to Slice
Slice Control
LatticeXP2 Family Data Sheet
Architecture
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