P87LPC761BN NXP Semiconductors, P87LPC761BN Datasheet - Page 30

• Manufacturer Part Number: P87LPC761BN
• Description: IC, MCU 8BIT 80C51 2K OTP, DIP16
• Manufacturer: NXP Semiconductors

Specifications of P87LPC761BN

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 14
• Program Memory Size: 2KB
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Oscillator Type: External, Internal
• No. Of Timers: 2
• Digital: RoHS Compliant
• Package: 16PDIP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 14
• Interface Type: I2C/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when V
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with V
Reset
The P87LPC761 has an integrated power-on reset circuit which
always provides a reset when power is initially applied to the device.
It is recommended to use the internal reset whenever possible to
2002 Mar 07
Low power, low price, low pin count (16 pin)
microcontroller with 2 kbyte OTP
UCFG1.RPD = 1 (default)
SOFTWARE RESET
POWER MONITOR
SRST (AUXR1.3)
DD
WDTE (UCFG1.7)
MODULE
RPD (UCFG1.6)
is less than 4 V, but are required for a V
RESET
WDT
RST/V
PP
Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin
PIN
P1.5
Pin is used as
digital input pin
Internal power-on
Reset active
P87LPC761
Figure 21. Block Diagram Showing Reset Sources
DD
less than 4 V.
DD
UCFG1.RPD = 0
27
external active-low reset pin RST by programming the RPD bit in the
save external components and to be able to use pin P1.5 as a
general-purpose input pin.
The P87LPC761 can additionally be configured to use P1.5 as an
User Configuration Register UCFG1 to 0. The internal reset is still
active on power-up of the device. While the signal on the RST pin is
low, the P87LPC761 is held in reset until the signal goes high.
The watchdog timer on the P87LPC761 can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
UCFG1 is described in the System Configuration Bytes section of
this datasheet.
CLOCK
CPU
RST
Pin is used as
active-low reset pin
Internal power-on
Reset active
P87LPC761
RESET
TIMING
R
S
Q
SU01578
P87LPC761
CHIP RESET
SU01170
Preliminary data