SST25VF080B-50-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF080B-50-4I-QAF Datasheet - Page 16

• Manufacturer Part Number: SST25VF080B-50-4I-QAF
• Description: 8M FLASH MEMORY, SPI EEPROM, WSON-8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF080B-50-4I-QAF

• Memory Size: 8Mbit
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: WSON
• No. Of Pins: 8
• Svhc: No SVHC (18-Jun-2010)
• Package / Case: WSON
• Device: RoHS Compliant
• Memory Type: Flash
• Memory Configuration: 1M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes

Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
©2006 Silicon Storage Technology, Inc.
FIGURE 14: C
FIGURE 15: R
SCK
CE#
SO
SI
HIP
EAD
MODE 3
MODE 0
-E
-S
RASE
TATUS
MSB
0
S
-R
EQUENCE
1
EGISTER
HIGH IMPEDANCE
2
SCK
CE#
SO
3
(RDSR) S
SI
05
MODE 3
MODE 0
4
5
EQUENCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
16
60 or C7
7
by executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait T
for the completion of the internal self-timed Chip-Erase
cycle. See Figure 14 for the Chip-Erase sequence.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 15 for the RDSR instruction sequence.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
1296 ChEr.0
9
10
Register Out
11
Status
12
8 Mbit SPI Serial Flash
13
14
1296 RDSRseq.0
SST25VF080B
S71296-01-000
1/06
CE