SST25VF080B-50-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF080B-50-4I-QAF Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/6/610/silicon_storage_technology_sml.jpg)
SST25VF080B-50-4I-QAF
Manufacturer Part Number
SST25VF080B-50-4I-QAF
Description
8M FLASH MEMORY, SPI EEPROM, WSON-8
Manufacturer
SILICON STORAGE TECHNOLOGY
Datasheet
1.SST25VF080B-50-4I-S2AF.pdf
(28 pages)
Specifications of SST25VF080B-50-4I-QAF
Memory Size
8Mbit
Clock Frequency
50MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
WSON
No. Of Pins
8
Svhc
No SVHC (18-Jun-2010)
Package / Case
WSON
Device
RoHS Compliant
Memory Type
Flash
Memory Configuration
1M X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF080B-50-4I-QAF
Manufacturer:
SST
Quantity:
20 000
Data Sheet
TABLE 10: C
TABLE 11: R
TABLE 12: AC O
©2006 Silicon Storage Technology, Inc.
Parameter
C
C
Symbol
N
T
I
Symbol
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
LTH
DR
CLK
SCKH
SCKL
SCKR
SCKF
CES
CEH
CHS
CHH
CPH
CHZ
CLZ
DS
DH
HLS
HHS
HLH
HHH
HZ
LZ
OH
V
SE
BE
SCE
BP
OUT
IN
END
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
2. Maximum Rise and Fall time may be limited by T
3. Relative to SCK.
1
1
1
1
3
3
3
1
1
3
2
APACITANCE (T
ELIABILITY
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CE# Active Setup Time
CE# Active Hold Time
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
CE# High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
Data In Hold Time
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
Sector-Erase
Block-Erase
Chip-Erase
Byte-Program
PERATING
Description
Output Pin Capacitance
Input Capacitance
Parameter
Endurance
Data Retention
Latch Up
C
HARACTERISTICS
Parameter
C
A
= 25°C, f=1 Mhz, other pins open)
HARACTERISTICS
SCKH
and T
SCKL
Minimum Specification
Min
100
0.1
0.1
18
18
10
10
10
10
10
10
10
10
22
0
5
5
0
requirements
25 MHz
100 + I
10,000
100
DD
Max
25
15
20
15
25
25
15
50
10
Test Condition
Cycles
Units
Years
Min
0.1
0.1
50
mA
9
9
5
5
5
5
0
2
5
5
5
5
5
0
V
8 Mbit SPI Serial Flash
V
OUT
IN
50 MHz
= 0V
= 0V
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
Max
50
25
25
50
10
SST25VF080B
8
8
8
8
S71296-01-000
Maximum
12 pF
6 pF
Units
MHz
V/ns
V/ns
T10.0 1296
T11.0 1296
ms
ms
ms
T12.0 1296
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
1/06