CS5529-AS Cirrus Logic Inc, CS5529-AS Datasheet - Page 8

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CS5529-AS

Manufacturer Part Number
CS5529-AS
Description
A/D Converter (A-D) IC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5529-AS

Peak Reflow Compatible (260 C)
No
Termination Type
SMD
No. Of Bits
16 Bit
Leaded Process Compatible
No
Mounting Type
Surface Mount
No. Of Channels
2
Interface Type
Serial
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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SWITCHING CHARACTERISTICS
Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C
Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for
8
Master Clock Frequency:
Master Clock Duty Cycle
Rise Times
Fall Times
Start-up
Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing
Serial Clock Frequency
Serial Clock
SDI Write Timing
CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Read Timing
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
increased throughput.
external clock source.
Parameter
External Clock or Internal Oscillator
XTAL = 32.768 kHz (Note 21)
Any Digital Input Except SCLK
Any Digital Input Except SCLK
L
= 50pF)
(T
A
Any Digital Output
Any Digital Output
Pulse Width High
Pulse Width Low
= 25 °C; VA ± = ±2.5 V ±5%, VD+ = 3 V ±5% or 5 V ±5%;
(Note 20)
(Note 20)
(Note19)
SCLK
SCLK
Symbol
SCLK
XIN
t
t
t
t
rise
rise
por
ost
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
Min
250
250
100
100
30
40
50
50
0
-
-
-
-
-
-
-
-
-
-
-
32.768
1002
Typ
500
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
100
150
150
150
1.0
1.0
60
2
CS5529
-
-
-
-
-
-
-
-
-
-
DS246F1
cycles
MHz
Unit
kHz
XIN
ms
µs
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%

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