CS8406-CZ Cirrus Logic Inc, CS8406-CZ Datasheet - Page 16

• Manufacturer Part Number: CS8406-CZ
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8406-CZ

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Program Memory Type: 1 V
• Transceiver Type: Digital Audio
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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5. AES3 TRANSMITTER
The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme pro-
vides write access to the channel status and user data. This buffering scheme is described in
Appendix B: Channel Status and User Data Buffer Management.
The AES3 transmitter encodes and transmits audio and digital data according to the AES3,
IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multi-
plexed together and bi-phase mark encoded. The resulting bit stream is driven to an output con-
nector either directly or through a transformer. The transmitter is clocked from the clock input pin,
OMCK. If OMCK is asynchronous to the data source, an interrupt bit (TSLIP) is provided that will
go high every time a data sample is dropped or repeated.
The channel status (C) and user (U) bits in the transmitted data stream are taken from storage
areas within the CS8406. The user can manually access the internal storage or configure the
CS8406 to run in one of several automatic modes. Appendix B: Channel Status and User Data
Buffer Management provides detailed descriptions of each automatic mode and describes meth-
ods of manually accessing the storage areas. The transmitted user bit data can optionally be in-
put through the U pin, under the control of a control port register bit.
Figure 8 shows the C/U/V timing requirements.
5.1
The TCBL pin is used to control or indicate the start of transmitted channel status block bound-
aries and may be an input or an output.
In some applications, it may be necessary to control the precise timing of the transmitted AES3
frame boundaries. This may be achieved in two ways:
a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well
b) If the serial audio input port is in slave mode and TCBL is set to output, the start of the A chan-
5.2
The line drivers are low skew, low impedance, differential outputs capable of driving cables di-
rectly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock
is provided, and optionally under the control of a register bit. The CS8406 also allows immediate
muting of the AES3 transmitter audio data through a control register bit.
External components are used to terminate and isolate the external cable from the CS8406.
These components are detailed in “Appendix A: External AES3/SPDIF/IEC60958 Transmitter
Components” on page 39.
nel sub-frame will be aligned with the leading edge of ILRCK.
as a new channel status block start.
Transmitted Frame and Channel Status Boundary Timing
TXN and TXP Drivers
CS8406
DS580F1