CS8406-CZ Cirrus Logic Inc, CS8406-CZ Datasheet - Page 40

• Manufacturer Part Number: CS8406-CZ
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8406-CZ

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Program Memory Type: 1 V
• Transceiver Type: Digital Audio
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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15.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which
allows the user to manage the C and U data through the control port.
15.1 AES3 Channel Status(C) Bit Management
The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels
(192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these
RAM buffers through the control port.
The CS8406 manages the flow of channel status data at the block level, meaning that entire
blocks of channel status information are buffered at the input, synchronized to the output time-
base, and then transmitted. The buffering scheme involves a cascade of 2 block-sized buffers,
named E and F, as shown in Figure 16. The MSB of each byte represents the first bit in the serial
C data stream. For example, the MSB of byte 0 (which is at control port address 20h) is the con-
sumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F
buffer is used as the source of C data for the AES3 transmitter. The F buffer accepts block trans-
fers from the E buffer.
15.1.1 Accessing the E buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into
the register space of the CS8406, through the control port. The user can modify the data to be
transmitted by writing to the E buffer.
The user can configure the interrupt enable register to cause interrupts to occur whenever “E to
F” buffer transfers occur. This allows determination of the allowable time periods to interact with
the E buffer.
Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user
sets this bit. This may be used whenever “long” control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in Figure 17. For writing, the sequence
starts after a E to F transfer, which is based on the output timebase.
Figure 16. Channel Status Data Buffer Structure
8 -bits
A
C on tro l Port
w o rds
E
8 -b its
24
B
Tran sm it
D a ta
Bu ffer
F
To
AES3
Tra nsm itte r
CS8406
DS580F1