CS8406-CZ Cirrus Logic Inc, CS8406-CZ Datasheet - Page 31

• Manufacturer Part Number: CS8406-CZ
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8406-CZ

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Program Memory Type: 1 V
• Transceiver Type: Digital Audio
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS580F1
SDA/CDOUT
SCL/CCLK
AD0/CS
AD1/CDIN
AD2
RXP
INT
TCBL
U
TEST
28
27
19
15
20
10
11
16
17
18
1
2
3
4
7
8
Serial Control Data I/O (I²C Mode) / Data Out (SPI) ( Input/Output ) - In I²C Mode, SDA is the control I/O
data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI mode, CDOUT is the
output data from the control port interface on the CS8406
Control Port Clock ( Input ) - Serial control interface clock and is used to clock control data bits into and
out of the CS8406. In I²C mode, SCL requires an external pull-up resistor to VL.
Address Bit 0 (I²C Mode) / Control Port Chip Select (SPI) ( Input) - A falling edge on this pin puts the
CS8406 into SPI control port mode. With no falling edge, the CS8406 defaults to I²C mode. In I²C mode,
AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8406
Address Bit 1 (I²C Mode) / Serial Control Data in (SPI) ( Input ) - In I²C mode, AD1 is a chip address
pin. In SPI mode, CDIN is the input data line for the control port interface.
Address Bit 2 (I²C Mode) ( Input ) - Determines the AD2 address bit for the control port in I²C mode, and
should be connected to GND or VL. If SPI mode is used, the AD2 pin should be connected to either
GND or VL.
Auxiliary AES3 Receiver Port ( Input ) - Input for an alternate, already AES3 coded, audio data
Interrupt ( Output ) - Indicates key events during the operation of the CS8406. All bits affecting INT may
be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt
are readable in the control registers. The polarity of the INT output, as well as selection of a standard or
open drain output, is set through a control register. Once set true, the INT pin goes false only after the
interrupt status registers have been read and the interrupt status bits have returned to zero.
Transmit Channel Status Block Start ( Input / Output ) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
User Data ( Input ) - May optionally be used to input User data for transmission by the AES3 transmitter,
see
pin. If the U pin is driven by a logic level output, then a 100 Ω series resistor is recommended.
Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or
GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how-
ever current consumption from VL will increase by 25 µA per TEST pin that is left floating.
Figure 4
for timing information. If not driven, a 47 kΩ pull-down resistor is recommended for the U
CS8406
source.
31