DSPIC30F6011A-20E/PT Microchip Technology, DSPIC30F6011A-20E/PT Datasheet - Page 28

• Manufacturer Part Number: DSPIC30F6011A-20E/PT
• Description: Digital Signal Processor
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6011A-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 132KB (44K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F5011/5013
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
FIGURE 3-6:
DS70116J-page 28
Optionally
Mapped
into Program
Memory
Data Address Space
DATA SPACE MEMORY MAP
2 Kbyte
SFR Space
SRAM Space
4 Kbyte
DATA SPACE MEMORY MAP
Address
MSB
0x1FFF
0x0001
0x07FF
0x0801
0x0FFF
0x1001
0x17FF
0x1801
0x8001
0xFFFF
MSB
Unimplemented (X)
Y Data RAM (Y)
X Data RAM (X)
16 bits
SFR Space
X Data
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64-
Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64 Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
The MAC class instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
The data space memory map is shown in
The X data space is used by all instructions and supports
all addressing modes, as shown in
LSB
0x0000
0x07FE
0x0800
0x0FFE
0x1000
0x17FE
0x1800
0x1FFE
0x8000
0xFFFE
Address
LSB
© 2011 Microchip Technology Inc.
Figure
8 Kbyte
Near
Data
Space
3-7.
Figure
3-6.