PIC16C926-I/PT Microchip Technology, PIC16C926-I/PT Datasheet - Page 69

• Manufacturer Part Number: PIC16C926-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C926-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C926I/PT

Figure 9-11 and Figure 9-12 show master-transmitter
and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a Repeated START
condition (Sr) must be generated. This condition is
identical to the START condition (SDA goes high-to-low
FIGURE 9-11:
FIGURE 9-12:
FIGURE 9-13:
Sr
A master reads a slave immediately after the first byte.
Transfer direction of data and Acknowledgment bits depends on R/W bits.
Combined format - A master addresses a slave with a 10-bit address, then transmits
2001 Microchip Technology Inc.
For 7-bit address:
Combined format:
A master-transmitter addresses a slave-receiver with a
7-bit address. The transfer direction is not changed.
S
S
For 7-bit address:
Slave Address
S
From slave to master
From master to slave
Slave Address R/W A Data A Data A P
Slave Address R/W A Data A/A Sr
From slave to master
From master to slave
First 7 bits
Slave Address R/W A Data A Data A/A P
From slave to master
From master to slave
'1' (read)
'0' (write)
(write)
(read)
R/W A
data to this slave and reads data from this slave.
MASTER-TRANSMITTER SEQUENCE
MASTER-RECEIVER SEQUENCE
COMBINED FORMAT
(n bytes - Acknowledge)
(n bytes - Acknowledge)
Slave Address
Second byte
data transferred
data transferred
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
S = START Condition
P = STOP Condition
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
S = START Condition
P = STOP Condition
Sr = repeated
START Condition
S = START Condition
P = STOP Condition
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
(n bytes + Acknowledge)
(read or write)
Slave Address R/W A Data A/A
A
Data
Preliminary
A
(write)
Data A/A
For 10-bit address:
S
while SCL is high), but occurs after a data transfer
Acknowledge pulse (not the bus-free state). This allows
a master to send “commands” to the slave and then
receive the requested information, or to address a dif-
ferent slave device. This sequence is shown in
Figure 9-13.
For 10-bit address:
S
Slave Address
Direction of transfer
may change at this point
Slave Address
First 7 bits
First 7 bits
A master-transmitter addresses a slave-receiver
with a 10-bit address.
A master-transmitter addresses a slave-receiver
with a 10-bit address.
Sr Slave Address
Sr
Slave Address
(write)
Data A
First 7 bits
(write)
First 7 bits
P
PIC16C925/926
R/W A1 Slave Address
R/W A1 Slave Address
(read)
(read)
Data
R/W A Data A
R/W A3
Second byte
Second byte
A/A
P
Data A
DS39544A-page 67
A2
A2
Data
Data
A
A P
P