PIC16F913-E/SS Microchip Technology, PIC16F913-E/SS Datasheet - Page 142

• Manufacturer Part Number: PIC16F913-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F913-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SSP, I2C, AUSART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F913/914/916/917/946
9.3.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 9.3.1.4 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
TABLE 9-9:
DS41250F-page 140
INTCON
LCDCON
LCDSE1
PIE1
PIR1
RCREG
RCSTA
SSPCON
TRISC
TXSTA
Legend:
never Idle
Name
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
AUSART Receive Data Register
TRISC7
LCDEN
WCOL
CSRC
AUSART Synchronous Slave
Reception
SPEN
SE15
Bit 7
EEIE
EEIF
GIE
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
TRISC6
SSPOV
SLPEN
SE14
ADIE
Bit 6
PEIE
ADIF
RX9
TX9
TRISC5
SSPEN
WERR
SREN
TXEN
SE13
RCIE
RCIF
Bit 5
T0IE
VLCDEN
TRISC4
CREN
SYNC
SE12
INTE
Bit 4
TXIE
TXIF
CKP
ADDEN
TRISC3
SSPM3
SSPIE
SSPIF
RBIE
SE11
Bit 3
CS1
—
CCP1IE
CCP1IF
TRISC2
SSPM2
BRGH
FERR
SE10
9.3.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 2
T0IF
CS0
Set the SYNC and SPEN bits and clear the
CSRC bit.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
Set the CREN bit to enable reception.
The RCIF bit of the PIR1 register will be set
when reception is complete. An interrupt will be
generated if the RCIE bit of the PIE1 register
was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register.
TMR2IE
TMR2IF
TRISC1
LMUX1
SSPM1
OERR
TRMT
Bit 1
INTF
SE9
Synchronous Slave Reception
Set-up:
TMR1IE
TMR1IF
TRISC0
SSPM0
LMUX0
RX9D
TX9D
Bit 0
RBIF
SE8
© 2007 Microchip Technology Inc.
0000 000x
0001 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 000X
0000 0000
1111 1111
0000 -010
POR, BOR
Value on
0000 000x
0001 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 000X
0000 0000
1111 1111
0000 -010
Value on
all other
Resets