PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 48

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
4.7.1
PIC18C601/801 devices have four two-word instruc-
tions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the four MSB’s set to 1’s
and is a special kind of NOP instruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC and
skips one instruction. A program example that demon-
strates this concept is shown in Example 4-3. Refer to
Section 19.0 for further details of the instruction set.
4.8
Lookup tables are implemented two ways:
• Computed GOTO
• Table Reads
4.8.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before exe-
cuting a call to that table. The first instruction of the called
routine is the ADDWF PCL instruction. The next instruc-
tion executed will be one of the RETLW 0xnn instruc-
tions that returns the value 0xnn to the calling function.
EXAMPLE 4-3:
DS39541A-page 48
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
Object Code
Object Code
Lookup Tables
TWO-WORD INSTRUCTIONS
COMPUTED GOTO
Two-Word Instructions
TSTFSZ
MOVFF
ADDWF
TSTFSZ
MOVFF
ADDWF
Advance Information
REG1
REG1, REG2
REG3
REG1
REG1, REG2
REG3
PCL
CASE 1:
CASE 2:
; is RAM location 0?
; No, execute 2-word instruction
; 2nd operand holds address of REG2
; continue code
; is RAM location 0?
; Yes
; 2nd operand executed as NOP
; continue code
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
4.8.2
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored as 2 bytes per pro-
gram word by using table reads and writes. The table
pointer (TBLPTR) specifies the byte address and the
table latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is trans-
ferred to/from program memory one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 6.0.
Warning: The LSb of the PCL is fixed to a value of ‘0’.
Note:
Source Code
Source Code
Hence, computed GOTO to an odd address
is not possible.
If execution is taking place from Boot RAM
Program Memory, RETLW instructions
must be used to read lookup values from
the Boot RAM itself.
TABLE READS/TABLE WRITES
2001 Microchip Technology Inc.