PIC18F2431-I/MM Microchip Technology, PIC18F2431-I/MM Datasheet - Page 213
![16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2431-I/MM
Manufacturer Part Number
PIC18F2431-I/MM
Description
16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18F2431-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Request inventory verification / Request inventory verification
Other names
PIC18F2431-I/ML
PIC18F2431-I/ML
PIC18F2431-I/ML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2431-I/MM
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F2431-I/MM
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- Current page: 213 of 392
- Download datasheet (4Mb)
19.3.1.1
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-Bit Addressing mode, two address bytes need to
be received by the slave
Significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the
second address byte. For a 10-bit address, the first
byte would equal ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
TABLE 19-2:
2010 Microchip Technology Inc.
Note:
Transfer is Received
Status Bits as Data
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
SSP Interrupt Flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
BF
0
1
1
0
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
Addressing
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
(Figure
SSPSR SSPBUF
19-7). The five Most
Yes
No
No
No
PIC18F2331/2431/4331/4431
The sequence of events for 10-Bit Addressing mode is
as follows, with Steps 7-9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Generate ACK
Receive first (high) byte of address (SSPIF, BF
and UA bits are set).
Update the SSPADD register with second (low)
byte of address (clears bit, UA, and releases the
SCL line).
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit, UA.
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (SSPIF and
BF bits are set).
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Pulse
Yes
No
No
No
(SSP interrupt occurs
Set SSPIF Bit
if enabled)
DS39616D-page 213
Yes
Yes
Yes
Yes
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