PIC18F2431-I/MM Microchip Technology, PIC18F2431-I/MM Datasheet - Page 311
![16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2431-I/MM
Manufacturer Part Number
PIC18F2431-I/MM
Description
16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18F2431-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Request inventory verification / Request inventory verification
Other names
PIC18F2431-I/ML
PIC18F2431-I/ML
PIC18F2431-I/ML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2431-I/MM
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F2431-I/MM
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- Current page: 311 of 392
- Download datasheet (4Mb)
NEGF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Negate f
[ label ]
0 f 255
a [0,1]
( f ) + 1 f
N, OV, C, DC, Z
Location, ‘f’, is negated using two’s
complement. The result is placed in the
data memory location, ‘f’. If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1
NEGF
Read
0110
Q2
0011 1010 [0x3A]
1100 0110 [0xC6]
NEGF
REG, 1
110a
Process
Data
Q3
f [,a]
ffff
register ‘f’
PIC18F2331/2431/4331/4431
Write
Q4
ffff
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
None.
Decode
Q1
operation
No Operation
[ label ]
None
No operation
None
No operation.
1
1
0000
1111
No
Q2
NOP
0000
xxxx
operation
No
Q3
DS39616D-page 311
0000
xxxx
operation
No
Q4
0000
xxxx
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