PIC18F2431-I/MM Microchip Technology, PIC18F2431-I/MM Datasheet - Page 37
![16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2431-I/MM
Manufacturer Part Number
PIC18F2431-I/MM
Description
16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18F2431-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Request inventory verification / Request inventory verification
Other names
PIC18F2431-I/ML
PIC18F2431-I/ML
PIC18F2431-I/ML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2431-I/MM
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F2431-I/MM
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- Current page: 37 of 392
- Download datasheet (4Mb)
3.7.2
The PIC18F2331/2431/4331/4431 devices contain
circuitry to prevent clocking “glitches” when switching
between clock sources. A short pause in the system
clock occurs during the clock switch. The length of this
pause is between 8 and 9 clock periods of the new
clock source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed
3.8
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator using
the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin,
if used by the oscillator) will stop oscillating.
When the device executes a SLEEP instruction, the
system is switched to one of the power-managed
modes, depending on the state of the IDLEN and
SCS<1:0> bits of the OSCCON register. See
Section 4.0 “Power-Managed Modes”
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power-managed mode (see
Timer (WDT)”
Monitor”). The INTOSC output at 8 MHz may be used
TABLE 3-3:
Note:
2010 Microchip Technology Inc.
RC, INTIO1
RCIO, INTIO2
ECIO
EC
LP, XT and HS
secondary
Effects of Power-Managed Modes
on the Various Clock Sources
See
OSCILLATOR TRANSITIONS
OSC Mode
Table 5-1
through
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
clock
Section 23.4 “Fail-Safe Clock
in
Section 5.0 “Reset”
modes
Section 23.2 “Watchdog
(SEC_RUN
Floating, external resistor
should pull high
Floating, external resistor
should pull high
Floating, pulled by external clock
Floating, pulled by external clock
Feedback inverter disabled at
quiescent voltage level
for details.
Modes”.
PIC18F2331/2431/4331/4431
for time-outs due to Sleep and MCLR Reset.
and
OSC1 Pin
directly to clock the system, or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a system clock source (i.e., SSP slave,
INTx pins, A/D conversions and others).
3.9
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal
circumstances, and the primary clock is operating and
stable. For additional information on power-up delays,
see
Section 5.4 “Brown-out Reset
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the crys-
tal oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
Section 5.3 “Power-on Reset (POR)”
26-8), if enabled, in Configuration Register 2L.
Power-up Delays
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled at
quiescent voltage level
OSC2 Pin
(BOR)”.
DS39616D-page 37
through
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